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InAs High Electron Mobility Transistors with Buried Gate for Ultralow-Power-Consumption
Low-Noise Amplifier Application
View the table of contents for this issue, or go to the journal homepage for more 2008 Jpn. J. Appl. Phys. 47 7119
(http://iopscience.iop.org/1347-4065/47/9R/7119)
InAs High Electron Mobility Transistors with Buried Gate
for Ultralow-Power-Consumption Low-Noise Amplifier Application
Chien-I KUO, Heng-Tung HSU1, Edward Yi CHANG, Yasuyuki MIYAMOTO2, and Wen-Chung TSERN Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu, Taiwan 30010, R.O.C.
1Department of Communications Engineering, Yuan Ze University, Chungli, Taiwan 32003, R.O.C.
2Department of Physical Electrons, Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo 152-8552, Japan
(Received March 19, 2008; accepted May 13, 2008; published online September 12, 2008)
An InAs/In0:7Ga0:3As composite channel high-electron-mobility transistor (HEMT) fabricated using the gate sinking
technique was realized for ultralow-power-consumption low-noise application. The device has a very high transconductance of 1900 mS/mm at a drain voltage of 0.5 V. The saturated drain–source current of the device is 1066 mA/mm. A current gain cutoff frequency ( fT) of 113 GHz and a maximum oscillation frequency ( fmax) of 110 GHz were achieved at only drain bias
voltage Vds¼0:1 V. The 0:08 40mm2device demonstrated a minimum noise figure of 0.82 dB and a 14 dB associated gain
at 17 GHz with 1.14 mW DC power consumption. [DOI:10.1143/JJAP.47.7119]
KEYWORDS: InAs/InGaAs, gate sinking, current gain cutoff frequency ( fT), ultralow power
Low-noise amplifiers (LNAs) with extremely low DC power consumption have always been considered as critical components for various emerging wireless communication applications including mobile radio systems and handheld imagers. Among all the possible technologies that meet the stringent system requirements, high-indium-content InP-based InAlAs/In1xGaxAs high electron mobility transistors (HEMTs) are particularly promising because they provide higher electron mobility, higher saturation velocity, and higher sheet electron densities which lead to incomparable speed-power device performance with competing technolo-gies such as GaAs HEMTs.1–3)
In general, high electron mobility and conductivity are essential for devices to have high drive currents at both low drain (IDLIN) and high drain (IDSAT) biases, which are very critical to maintain excellent RF performance with extreme-ly low DC power consumption.4,5) In the effort of minimiz-ing noise figure of devices, several approaches have been adopted, as described in the references. Since noise figure is directly related to the gate length (Lg) and gate resistance (Rg), reduction of these two parameters has been the principle in achieving extremely low noise figure of devices. While reduction of gate length seems to be a good approach, the limitation of such an approach lies mainly in the degradation of performance caused by the short channel effect. Thus, care must be taken in obtaining the optimum physical parameters of devices for such applications.2)
Pt-based gate sinking technology has been widely applied in the fabrication of HEMTs since it provides a promising solution that enables vertical scaling of gate-to-channel distance without increasing access resistance. On the other hand, the short-channel effect can also be minimized.6,7) Another advantage of using a Pt-based structure is the relatively larger Schottky barrier height, which in turn suppresses gate leakage current.8)In this study, we devel-oped 80 nm gate InAs/In0:7Ga0:3As composite channel HEMTs using the Pt-buried gate technique with excellent DC and RF performances for ultralow-power low-noise applications.
In the HEMT structure, InxAl1xAs was used as the buffer layer, which was grown by the molecular beam epitaxy (MBE) method on a 2-in. InP substrate. The epitaxial structure of the device is shown in Fig. 1. The following
process flow describes the sequence of device fabrication. The active area of the device was isolated by wet chemical mesa etching. After that, the 3 mm source–drain (S–D) spacing ohmic contacts were formed by evaporating Au/Ge/ Ni/Au on a heavily doped n-InGaAs cap layer and then alloyed at 250C using rapid thermal annealing (RTA) system. The contact resistance and sheet resistance measured using the transmission line model (TLM) were 0.021 mm and 37.4 /, respectively. To process the T-shaped gate, the 50 kV JEOL electron beam lithography system (JBX 6000 FS) of 100 pA beam current was used with a conven-tional trilayer e-beam resist consisting of ZEP-520/PMGI/ ZEP-520. After gate recess, the Pt (12 nm)/Ti (60 nm)/ Pt (80 nm)/Au (180 nm) were deposited as Schottky gate metal and lifted off using a ZDMAC remover (ZEON) to form a 80 nm T-shaped gate. Devices were passivated with 1000 A˚ silicon nitride film by plasma-enhanced chemical vapor deposition (PECVD). Finally, thermal annealing at 250C for 3 min in forming gas ambient was performed for gate sinking to further recess the channel. The access resistance increased from 0.021 mm to 0.032 mm during gate sinking, the change was negligible and the characteristics of the device did not degrade.
The drain–source current Ids versus drain–source voltage Vds curves and the dc transconductance (gm) versus gate voltage at different Vdsvalues of the 80 nm gate, 2 20 mm2 width InAs/In0:7Ga0:3As composite channel HEMT with gate sinking are shown in Figs. 2(a) and 2(b), respectively. The device exhibits a very high drain current density (1066 mA/mm), which is mainly attributed to a very low contact resistance and the superior electron mobility in the InAs channel.
Additionally, very high gm values at low drain voltages were achieved due to the reduction of distance between the gate and the channel resulting from the gate sinking process. A peak of gm 1900 mS/mm at Vds¼0:5 V was observed. Care must be taken in the biasing of such devices with a very small energy bandgap since the impact ionization phenom-enon would occur at a high drain bias level, which in turn causes serious performance degradation. S-parameter meas-urement was performed from 5 to 80 GHz using a Cascade Microtech on-wafer probing system with a vector network analyzer, and a standard load-reflection-reflection-match Japanese Journal of Applied Physics
Vol. 47, No. 9, 2008, pp. 7119–7121 #2008 The Japan Society of Applied Physics
7119
(LRRM) calibration method was used to calibrate the measurement system. The reference plane of calibration was set at the tips of the probes. To accurately evaluate the performance of the intrinsic device, the parasitic effects due to the probing pads were carefully de-embedded from the measured S-parameters using the same method as that described in ref.9and the equivalent circuit model
describ-ed in ref.10. The maximum frequency of oscillation fmaxof a 2 20 mm2 device peaked at 214 GHz, at gate and drain bias of 0:3 and 0.3 V, respectively [see Fig. 3(a)]. The corresponding cutoff frequency fT at this bias point was 250 GHz.
In evaluating the devices for ultralow-DC-power-con-sumption applications, the devices were biased at 0.1 V and the RF performance of the devices was characterized. As shown in Fig. 3(b), a reasonable fT= fmax of 113/110 GHz was achieved at low bias levels. The total DC power consumptions were 5.10 and 0.35 mW when biased at peak fT and fmax, respectively. These excellent RF performances resulted from reduced gate-to-channel distance by the gate sinking process. This reduction of gate-to-channel distance through gate sinking tends to suppress the short-channel effect and enhances the overshooting in electron velocity. The noise performances at different drain voltage biases are shown in Figs. 4(a) and 4(b) with the frequency range from 1 to 17 GHz under optimum bias conditions. The measured minimum noise figures (NFmin) at 17 GHz were 0.82 and 1.05 dB for Vds¼0:3 and 0.1 V, respectively; in addition, the corresponding associated gains (Ga) were 14 and 8.6 dB, respectively.
In summary, the 80 nm T-gate InAs/In0:7Ga0:3As HEMTs fabricated by Pt gate sinking were characterized for ultra-low-power low-noise applications. With the epitaxial struc-ture of the device optimized, the reduction of gate-to-Fig. 1. (Color online) Epitaxial structure of the InAs HEMT device.
0.0 0 200 400 600 800 1000 1200
Drain current (mA
/mm)
Source drain voltage (V)
Vg = 0 Vg = -0.1 Vg = -0.2 Vg = -0.3 Vg = -0.4 Vg = -0.5 Vg = -0.6 Vg = -0.7 Vg = -0.8 (a) 0.1 0.2 0.3 0.4 0.5 -1.0 0 500 1000 1500 2000 T ransconductance (mS/mm) Vgs (V) Vd = 0.5 V Vd = 0.4 V Vd = 0.3 V Vd = 0.2 V Vd = 0.1 V (b) -0.8 -0.6 -0.4 -0.2 0.0
Fig. 2. (Color online) (a) The drain–source current Ids vs drain–source
voltage Vds curves and (b) the dc transconductance (gm) versus gate
voltage curves at different Vds, the device size is 80 nm 40 mm with gate
sinking. 1 0 5 10 15 20 25 30 35 40 fmax= 214 GHz fT = 250 GHz Gain (dB) Frequency (GHz) H21 MAG/MSG VDS = 0.3 V VGS = -0.3 V ID = 17 mA (a) 10 100 1 0 5 10 15 20 25 fmax = 110 GHz fT = 113 GHz Gain (dB) Frequency (GHz) H 21 MAG/MSG VDS = 0.1 V V GS = -0.5 V ID = 3.5 mA (b) 10 100
Fig. 3. (Color online) Maximum frequency of oscillation ( fmax) and
corresponding cutoff frequency fTof 80 nm 40 mm device at different
drain biases.
Jpn. J. Appl. Phys., Vol. 47, No. 9 (2008) C.-I KUOet al.
channel distance was achieved by the gate sinking process. The device exhibited a very high drain current density of 1066 mA/mm at Vds¼0:5 V, with a maximum gm of 1900 mS/mm. It also exhibited an fT of 113 GHz and an
fmaxup to 110 GHz at Vds¼0:1 V. Measured noise perform-ance revealed that the devices had a very low noise figure of 1.05 dB with an 8.6 dB associated gain at 17 GHz with only 0.25 mW DC power consumption. These state-of-the-art results demonstrate the potential of InAs HEMT for ultra-low-power and low-noise applications.
Acknowledgments
The authors would like to acknowledge the assistance and support of the National Science Council, and the Ministry of Economic Affairs, Taiwan, R.O.C., under the contracts NSC 96-2752-E-009-001-PAE and 95-EC-17-A-05-S1-020. Part of this work was supported by the ‘‘Nanotechnology Network Project’’ of the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan.
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10 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Frequency (GHz) Noise Figure NF (dB) 0 5 10 15 20 25 30 NF Ga 20 V
ds = 0.3 V Device with gate sinking I ds = 3.80 mA PDC = 1.14 mW NF Associated Gain Ga (dB) (a) 10 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 20 V
ds = 0.1 V Device with gate sinking Ids = 2.52 mA PDC = 0.25 mW Frequency (GHz) Noise Figure NF (dB) 0 5 10 15 20 NF Ga NF Associated Gain Ga (dB) (b)
Fig. 4. (Color online) Measured noise performance of device under various bias conditions (a) with Vds¼0:3 V, Ids¼3:80 mA/mm and
(b) with Vds¼0:1 V, Ids¼2:52 mA/mm.
Jpn. J. Appl. Phys., Vol. 47, No. 9 (2008) C.-I KUOet al.
