IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 3, MARCH 2000 113
Gate Oxide Integrity of Thermal Oxide Grown on
High Temperature Formed Si
0:3
Ge
0:7
Y. H. Wu and Albert Chin, Senior Member, IEEE
Abstract—We have investigated the gate oxide integrity of
thermal oxides direct grown on high temperature formed Si0 3Ge0 7. Good oxide integrity is evidenced by the low inter-face-trap density of 5 9 1010 eV 1cm 2, low oxide charge density of 5 6 1010 cm 2, and the small stress-induced leakage current after −3.3 V stress for 10 000 s. The good gate oxide integrity is due to the high temperature formed and strain-relaxed Si0 3Ge0 7 that has a original smooth surface and stable after subsequent high temperature process.
Index Terms—Gate oxide integrity, SiGe oxide, stress-induced
leakage current.
I. INTRODUCTION
G
ATE oxide integrity [1]–[6] is one of the most important factors for process integration. Although SiGe channel p-MOSFET’s [5]–[11] have improved current-drive capability, operation speed, and package density of CMOS circuits, the gate oxide integrity is still unexamined. To prevent strain relaxation and defect generation, low temperature ( ) processing is necessary for SiGe p-MOSFET. Unfortunately, both gate oxide integrity and junction leakage are much degraded at the limited low temperature [12], and also obstacles further process inte-gration with modern high-K gate dielectric [13], [14]. Recently, we developed a new SiGe formation process using deposited amorphous Ge followed by rapid thermal annealing (RTA) [15]. Because SiGe is formed by solid phase epitaxy at high temper-atures similar to silicide formation [16], better thermal stability can be expected. High hole mobility of 250 cm /Vs and low source-drain p n junction leakage are obtained using high tem-perature (950 C) RTA of B implanted damages [17]. In this letter, we have further investigated the gate oxide integrity of thermal oxide directly grown on high temperature formed SiGe. Good oxide integrity is evidenced by low interface-trap den-sity, smooth surface, and small stress-induced leakage current (SILC), which is attributed to the high SiGe forming tempera-ture and no rough surface or pinholes [9]–[11] are formed during subsequent device processing.II. EXPERIMENTAL
Standard 4-in p-type (100) Si wafers were used in this work. In addition to SiGe oxides, Si control oxides were also
fabri-Manuscript received August 2, 1999; revised November 29, 1999. This work was supported by the National Science Council, Taiwan, R.O.C., under Contract 89-2215-E-009-044 . The review of this paper was arranged by Editor D. J. Dumin.
The authors are with the Department of Electronics Engineering, Na-tional Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: achin@cc.nctu.edu.tw).
Publisher Item Identifier S 0741-3106(00)02112-1.
Fig. 1. I–V characteristics of 50 Å thermal oxides grown on 850 and 900
C RTA formed Si Ge . The insert figure is the cumulative probability for
breakdown electric field.
cated as references. After device isolation, 120 Å amorphous Ge layer is deposited on active region. An HF-vapor passiva-tion is used to suppress the native oxide formapassiva-tion before Ge deposition [3], [14]–[17]. A 200 Å Si Ge with good crys-talline quality was then formed by RTA at 900 C as measured by cross-sectional TEM and X-ray diffraction. More detailed ma-terial characterization can be found in our previous study [16], [17]. Gate oxides of 50 Å were then grown by dry O at 900 C for both Si Ge and Si control sample. Gate capacitors were formed after a 3000 Å poly-Si deposition, phosphorus doping and subsequent patterning.
III. RESULTS ANDDISCUSSION
Fig. 1 shows current–voltage (I–V) characteristics of thermal oxides grown on 850 and 900 C RTA formed Si Ge , re-spectively. Inset figure is the cumulative probability for break-down electric field. Note that oxide grown on 850 C RTA SiGe has lower breakdown electric field as compared to that grown on 900 C SiGe. The degraded oxide property as decreasing SiGe formation temperature may be due to either strain relaxation or higher defect density by lower formation temperature. However, either mechanism may be a fundamental limitation of gate oxide integrity using low temperature MBE or CVD grown SiGe. A breakdown electric field of 11 MV/cm is obtained from thermal oxide grown on 900 C formed SiGe that is still lower than con-ventional SiO . Possible reason may be due to the presence of weaker GeO inside the SiO matrix as measured by SIMS sim-ilar to literature report [18]. However, the Ge peak decreases an order of magnitude within 10 Å from interface and most part of this oxide is primarily SiO form.
114 IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 3, MARCH 2000
Fig. 2. Interface-trap density of 50 Å thermal oxide as a function of energy obtained from the insert quasistatic and high frequency C–V curves.
Oxide charge and interface trap density are other important factors for gate oxide integrity, which are directly related to low frequency device noise [19]. Fig. 2 shows the interface-trap den-sity obtained from the insert capacitance–voltage (C–V) curves. A substrate doping concentration of cm is extracted from C–V that is consistent with the measured sheet resistivity on this wafer. A low interface-trap density of eV cm and a oxide charge density of cm are obtained that are the lowest reported values on direct thermally oxidized SiGe. The low concentration of oxide traps further explains the measured high interface hole mobility and current drive capability reported previously [17]. The negative oxide charge is believed to be due to the electron traps formed in SiGe oxide.
To further understand the low oxide traps, we have also measured the surface roughness using atomic force microscopy (AFM). Fig. 3(a) and (b) show the AFM images of Si Ge surface before and after oxidation, respectively. RMS rough-ness values of 1.55 and 1.60 Å are measured on respective Si Ge surface and oxide that indicates the oxidation process did not roughen the initial SiGe surface. It is also important to notice that the surface smoothness of Si Ge is comparable to standard Si surface. The smooth Si Ge surface may be due to the similar solid phase epitaxy as CoSi formation [16]. In contrast to previous reports, no rough surface or pinholes are observed even for a high Ge composition up to 70% [9]–[11]. This may be due to the high temperature formed Si Ge that is already strained relaxed as confirmed by the very sharp XRD linewidth after oxidation with near identical peak position and linewidth to as formed Si Ge .
Reliability is another important issue for practical process in-tegration of SiGe gate oxide. We have also investigated the re-liability using a constant voltage stress. Fig. 4 shows the SILC effect from the insert figure after a 3.3 V stress for 10 000 s. The small SILC indicates excellent gate oxide reliability that is attributed to the smooth oxide surface and related uniform elec-tric field distribution over oxide area [3]. The good reliability also suggests that the high temperature strain relaxed and stable Si Ge is the essential factor to achieve good oxide integrity.
IV. CONCLUSION
Good oxide integrity is obtained from direct thermally oxi-dized Si Ge . This is evidenced by low oxide-trap density,
(a)
(b)
Fig. 3. AFM images of 50 Å thermal oxide grown on Si Ge surface (a) before and (b) after oxidation.
Fig. 4. SILC effect after−3.3 V stress for 10 000 s on 50 Å thermal oxide grown on Si Ge . The insert figure is the current density during the stress.
smooth surface, and small SILC. The good gate oxide integrity is due to the high temperature formed and strain-relaxed Si Ge that has a very smooth surface and stable after subsequent high temperature process
ACKNOWLEDGMENT
The authors would like to thank K. C. Hsieh at the Department of Electrical Engineering, University of Illinois.
WU AND CHIN: GATE OXIDE INTEGRITY OF THERMAL OXIDE 115
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