Dual-metal-gate-integration complementary metal oxide semiconductor process scheme using Ru positive-channel metal oxide semiconductor and TaC negative-channel metal oxide semiconductor gate electrodes

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Dual-metal-gate-integration complementary metal oxide semiconductor process

scheme using Ru positive-channel metal oxide semiconductor and TaC

negative-channel metal oxide semiconductor gate electrodes

Wen-Tung Chang, Tsung-Eong Hsieh, and Chung-Ju Lee

Citation: Journal of Vacuum Science & Technology B 25, 1265 (2007); doi: 10.1116/1.2752516 View online: http://dx.doi.org/10.1116/1.2752516

View Table of Contents: http://scitation.aip.org/content/avs/journal/jvstb/25/4?ver=pdfcov Published by the AVS: Science & Technology of Materials, Interfaces, and Processing

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共Received 21 November 2006; accepted 30 May 2007; published 6 July 2007兲

This article presents the development of a wet removal process on the integration of complementary metal oxide semiconductor 共CMOS兲 dual metals with Ru for positive-channel metal oxide semiconductor and TaC for negative-channel metal oxide semiconductor on high-k HfO2 gate dielectric. The integration scheme focused on the wet etching capability for the first metal and the selectivity control on the high-k dielectrics under the metal gate. Using the developed chemical, ceric ammonium nitrate and nitric acid mixture used for Ru metal removal and HfO2 treated with Ar/ O₂plasma by selective diluted hydrofluoric wet etching, a CMOS dual-metal-gate structure was achieved with satisfactory device fabrication.

I. INTRODUCTION

The complementary metal oxide semiconductor共CMOS兲 dual-metal-gate process on bulk Si with two metal gate ma-terials using a gate-first approach is the main stream of present integration methodology. The candidate metals for both positive-channel metal oxide semiconductor 共PMOS兲 and negative-channel metal oxide semiconductor 共NMOS兲 rely on a proper integration scheme to implement on the Si wafer. According to the International Roadmap for Semiconductors,1the introduction of high dielectric constant 共high-k兲 gate materials and dual-metal-gate electrodes with appropriate work functions is demanded in the near future to reduce the gate direct tunneling leakage current2–6 and to eliminate boron 共B兲 penetration and polydepletion effect when the device scaling down is below 65 nm. In order to optimize the threshold voltage共Vt兲 in high performance

de-vices, a metal gate with tunable work function, about 4.1– 4.6 eV for NMOS and about 4.8– 5.1 eV for PMOS de-vices, is required for advanced transistor structures such as fin field effect transistors or ultrathin-body metal oxide semi-conductor field effect transistors.7–9Several approaches have been proposed, including a full silicided 共FUSI兲 metal gate,10–13 a midgap metal gate, and dual metal gates in CMOS integration.14–21FUSI is an extension of self-aligned silicide technology that has been widely used in CMOS de-vices. In a FUSI process, the poly-Si gate is totally silicided with the metal. The major advantage of the FUSI method is a CMOS compatible process integration. Among common silicides reported, NiSi FUSI has been demonstrated to have the best work function tunability and stable silicide/gate ox-ide interface. However, NiSi has the poorest thermal stability

and thermal treatment prior to silicidation process results in the incomplete elimination of boron penetration in p-channel device.22 Since the work function of the metal salicide can-not be modulated, a straightforward dual metal gate on the high-k dielectric CMOS process is hence proposed for N+-and P+-like gates in the 90 nm node or below. A versatile integration scheme has been developed which employs a wet etch process to remove the first metal selectively before de-positing the second metal. Zhang et al. reported TaSiN 共NMOS兲 and Ru 共PMOS兲 on HfO2, utilizing a TaSiN wet etch then following a dual-metal-gate dry etching process to fabricate the 85 nm devices.17 Lu et al. and Samavedam et

al. demonstrated Ti共NMOS兲, Mo 共PMOS兲, TaSiN 共NMOS兲,

TiN共PMOS兲 dual-metal-gate integration on Si3N4, and HfO2 gate dielectrics via the wet etching process, respectively.18,19 The semiconductor industry is feverishly investigating high-k materials with a low equivalent oxide thickness 共EOT兲 for the gate stack to replace SiO2 or SiON due to unacceptable leakage current when EOT is further scaled down. At present, the dielectric films based on hafnium ox-ides such as HfO2, HfAlO, HfSiO, HfON, and HfSiON are the leading contenders. There are also integration issues as depositing thin stoichiometric layers with acceptable electri-cal properties and then removing the high-k gate oxide with-out damaging the source and drain areas. Recently, plasma etching on HfO2gate dielectric was investigated23,24and ion implantation was found to enhance wet chemical etching of HfO₂.25However, further study is required on the etch selec-tivity of HfO2 over Si substrate for the integrated process control.

In this article, we demonstrate a dual-metal-gate CMOS flow with Ru共PMOS兲 and TaC 共NMOS兲 on HfO2. This flow utilizes a Ru wet etching process that is highly selective to high-k dielectric and a post-dual-metal-gate dry etching stop

a兲_{Author to whom correspondence should be addressed; electronic mail:}

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on HfO₂, then with Ar/ O₂plasma treatment and diluted hy-drofluoric 共HF兲共H₂O : 49% HF= 100: 1兲共DHF兲 wet etching process to subsequently remove the high-k dielectric to fab-ricate the 75 nm devices. The etching characteristics of the HfO₂ film with inductively coupled plasma based on the mechanism of ion energetic reactions and ion bombardment in Ar/ O2 were studied. Etching behaviors of various HfO2 films in DHF solution were also investigated.

II. EXPERIMENTAL DETAILS

A metal wet etching module shown in Fig. 1 was incor-porated into the conventional CMOS flow to fabricate Ru and TaC dual-metal-gate CMOS transistors. The high-k HfO₂ dielectrics about 2 nm thick was deposited first by atomic layer chemical vapor deposition at 350– 400 ° C then an-nealed in N2ambient at 700 ° C, followed by physical vapor deposition 共PVD兲 of about 10 nm the first metal 共Ru兲 for PMOS transistor electrode. A mask was used to define the PMOS then patterned with I-line共365 nm兲 photoresist which served as a protection layer at the PMOS area during the first metal wet removal. A solution containing ceric ammonium nitrate 共共NH4兲2Ce共NO3兲6兲 and nitric acid 共HNO3兲 mixture was applied for Ru metal to selectively remove from the NMOS area without damaging the photoresist and the

high-k underlayer. The photoresist was then removed by amine

base chemistry. Afterwards, the second metal共TaC兲 was de-posited by PVD process, followed with a 150 nm poly-capped with a tetraethoxysilane 共TEOS兲 hard mask deposi-tion. ArF共193 nm兲 photoresist was used to define the 75 nm gate length. The chlorine共Cl2兲 based chemistry was used for the TaC metal film etching, followed with an oxygen 共O2兲 based chemistry for the Ru film etching in a Lam etcher TCP-9400. During the Ru dry etching process, the HfO2 layer served as an etching stop to control the NMOS/PMOS

area loading. A subsequent DHF wet etching solution was used to remove the high-k dielectric with minimum Si sub-strate loss to achieve the device requirement.

To characterize the dual metal gate on the high-k dielec-tric gate structure, the stoichiometry, texture, phase, and etching rate of Ru on HfO₂ were examined by x-ray photo-electron spectroscopy 共XPS, VG Microlab-350兲, x-ray dif-fraction 共XRD, PANalytical X’pert Pro-MRD兲 with Cu K_␣ radiation, scanning electron microscopy共SEM, JEOL 6700F兲 operating at 10 keV, and transmission electron microscope 共TEM, Philips CM-200兲 operating at 200 keV, respectively. The cross-sectional TEM共XTEM兲 samples were prepared by focus ion beam 共FIB, FEI 235兲 operating at 30 kV with a gallium 共Ga兲 source and thinned to about 0.1␮m in thickness.

III. RESULTS AND DISCUSSION

The key process required for a dual-metal-gate integration relies on the successful wet removal of the first metal 共Ru兲 without damaging the high-k HfO2underlayer. In this study, with suitable adjustment of ceric ammonium nitrate/nitric acid ratio, the selectivity of Ru to HfO2could be controlled over 2800 without HfO2 loss after 10 nm Ru metal removal 共see in Table I兲. The capability of photoresist to protect the PMOS area was also one of the critical factors which must resist the wet etch during the Ru removal and should be removed easily after the first metal removal. Traditional O₂ plasma dry stripping is known to cause the damage when the HfO₂ dielectric surface is exposed during photoresist strip-ping. As shown in Figs. 2 and 3, amine based wet chemical stripping plays an important role as it removes the

photore-TABLEI. Selectivity control of chemicals for Ru wet removal.

Wet etching solution

Ru etching rate 共nm/min兲

HfO2etching rate

共nm/min兲共NH4兲2Ce共NO3兲6: HNO3= 6 : 1 70 0.06

共NH4兲2Ce共NO3兲6: HNO3= 50: 1 20 0.007

FIG. 1. CMOS dual-metal-gate fabrication integrates process flow: 共a兲 NMOS define with photoresist,共b兲 first metal wet etch, 共c兲 photoresist strip, and共d兲 second metal and polydeposition.

FIG. 2. SEM observation of photoresist removed by solvent:共a兲 before

pho-toresist removal and共b兲 after photoresist removal.

FIG. 3. High-resolution TEM inspection of HfO2thickness after Ru etching:

共a兲 deposited film subjected to post-700 °C annealed and 共b兲 after PR removal.

1266 Chang et al.: Dual-metal-gate integration CMOS process scheme 1266

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sist only but has no damage to the high-k dielectric. Post second metal and polydeposition indicated that the dual-metal-gate stack of NMOS/PMOS areas is well defined in this integration scheme, as shown Fig. 4. These high-resolution XTEM micrographs evidence that the interface between TaC and HfO2 is free of interfacial contamination. This indicates that the Ru wet etching with such scheme is suitable for the dual-metal-gate integration.

For NMOS/PMOS profile control during dual gate etch-ing step, the proposed HfO2etching was carried out by using the DHF wet removal method instead of dry plasma etching for the lower Si substrate damage and recess control. Before the high-k dielectric HfO2 wet removal, a high selectivity etching gas 共Ar/O2兲 was applied for PMOS area Ru dry etching and stopping on the HfO2layer, as shown in Fig. 5. Both NMOS and PMOS were well controlled to stop on the high-k dielectric layer after dry etching of Ru with Ar/ O2. In this study, by properly controlling the radio frequency 共rf兲 bias power during Ru metal dry etching step and the ex-tended over etching time with Ar/ O2 plasma bombardment could be contributed to remove the HfO₂ layer with DHF solution. The O₂gas that provided high etching selectivity of Ru metal and stopped on the HfO₂ layer that followed ex-tended overetching Ar/ O₂plasma implants of O ion through HfO₂into substrate resulted in faster DHF etching benefit. In practice, Fig. 6 reveals that the threshold rf bias power over 70 W is required to remove HfO₂film through the pretreat-ment condition of Ar/ O2 plasma bombardment for 90 s. In fact, that the bias power is related to ion plasma treated time combined sufficient energy for 4 nm HfO2 film

bombard-ment. The results shown in Fig. 6 also indicate that Si recess after post-DHF wet etching is controllable by rf bias power during Ar/ O2 plasma bombardment of HfO2 film surface treatment.

Four postsurface treatments for HfO2films, e.g., 500 and 700 ° C annealing in N2 ambient, Ar/ O2 plasma bombard-ment, and Ar/ O2bombardment followed by 700 ° C anneal-ing, were examined so as to identify their effects on DHF etching rate. As shown in Fig. 7, the increase of annealing temperature reduces the etching rate of HfO₂ film in DHF solution. This indicates that the etching rate decreases with the improvement of crystallinity of HfO₂film. Such a result is confirmed by XRD analyses shown in Fig. 8 which shows that the crystallinity of annealed HfO₂film is better than that of plasma bombarded films. Furthermore, due to the amor-phism generated by the plasma bombardment, the Ar/ O2 bombarded HfO2 film hence possesses the fastest etching rate in comparison with the HfO2 films subjected to other treatments. However, the plasma bombarded HfO2 became difficult to be etched away by DHF solution after a subse-quent 700 ° C anneal which caused the recrystallization of HfO2 film. The Ar/ O2 plasma bombardment induces physi-cal transformation in HfO2film that may accelerate the rem-edy of crystallinity of HfO2 film during subsequent thermal treatment. The HfO2 film subjected to Ar/ O2 bombardment FIG. 4. Post second metal deposition: 共a兲 NMOS:TaC/HfO₂ and 共b兲

PMOS: TaC / Ru/ HfO2.

FIG. 5. Post-dual-metal-gate etched stop on HfO2:共a兲 NMOS:TaC/HfO2

and共b兲 PMOS:TaC/Ru/HfO2. The gate surfaces are passivated with oxide,

Pt–Pd, and carbon coating for XTEM specimen fabrication with FIB.

FIG. 6. Correlation between bombardment parameters and HfO2 was

re-moved in 100:1 diluted HF solution for 60 s. The HfO2films are examined

with 4 nm thickness.

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followed by 700 ° C annealing hence exhibits the lowest etching rate in DHF solution. Hence, not only plasma treat-ment time but also rf bias power benefits from complete physical transformation resulting in a near completely amor-phous HfO2film which can be completely removed by DHF solution.

To get a complete look at the differences between the two HfO2films which are annealed with 700 ° C and post-Ar/ O2 plasma treatment, the high-resolution regions of O 1s and Hf 4f were examined. According to the result of XPS analyses of annealed and Ar/ O2plasma bombarded HfO2films shown in Fig. 9, the O 1s subpeak at 534.2 eV disappears after Ar/ O2bombardment whereas the O to Hf atomic concentra-tion ratio increased followed by O ion implementaconcentra-tion, sug-gesting the occurrence of phase transition. The atomic

con-centration ratio was calculated from the photoelectron peak areas by subtracting a linear-type background. In addition, a correlation with XRD confirmed that the HfO2 films are amorphousized by Ar/ O2plasma bombardment due to phase transition and benefited by DHF etching. The Ar/ O2plasma processing contributes to chemical shift of O 1s spectra from high bonding energy peak of crystalline shifted to lower bonding energy peak of amorphous HfO2. Again, this indi-cates that the amorphism of high-k HfO2 dielectrics sub-jected to Ar/ O2plasma bombarded film benefits its wet etch-ing in DHF solution. Both NMOS and PMOS gate profiles are shown in Fig. 10; those high-k HfO2films under gate are defined by following with pretreatment condition of Ar/ O2/ 90 s under 70 W rf bias power then post-HfO2 etched by 100:1 dilute HF for 60 s. The source-drain area gate poly, metal, and high-k dielectric layers are successfully defined by this dual-metal-gate process scheme.

IV. CONCLUSIONS

The dual-metal-gate CMOS devices are demonstrated with Ru and TaC gate electrodes on high-k HfO2 Key pro-cess modules such as a highly selective metal wet etching FIG. 8. XRD intensity ratio analysis of HfO2after Ar/ O2bombarded

treat-ment. The amorphous HfO₂ phase increased after Ar/ O₂ plasma bombardment.

FIG. 9. XPS Hf 4f and O 1s spectra from annealed and Ar/ O2plasma bombarded HfO2. The O / Hf atomic ratio increased after Ar/ O2plasma bombardment.

FIG. 10. Post-HfO2 etching with 100:1 dilute HF solution for 60 s: 共a兲

NMOS: TaC / HfO2and共b兲 PMOS:TaC/Ru/HfO2.

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substrate damage. Well-behaved CMOS transistors with gate length down to 75 nm indicate that these process modules can be readily utilized to fabricate the dual-metal-gate CMOS for below 65 nm node.

ACKNOWLEDGMENTS

This work was supported by the National Science Council of Taiwan 共Grant No. NSC 93–2216–E–009–008兲. The au-thors sincerely thank Applied Material Co. and FSI Co. for their support in ALPCVD, PVD, and wet bench equipment.

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