Abstract— Low-temperature (170 °C) Cu/In wafer-level and chip-level bonding for good thermal budget has been successfully developed for 3-D integration applications. For the well-bonded interconnect, Cu2In and Cu7In3phases with high melting
tem-perature of 388.3 °C and 632.2 °C can be formed, indicating high thermal stability. In addition, stable low specific contact resistance of bonded interfaces can be achieved with the values of approximately 0.3 × 10−8 -cm2. In addition to excep-tional electrical characteristics, the results of electrical reliability assessments including current stressing, temperature cycling, and unbiased HAST show excellent stability of Cu/In bonds without obvious deterioration. The low-temperature Cu/In bond-ing technology presents good bond quality and electrical performance, and possesses a great potential for future appli-cations of 3-D interconnects.
Index Terms— 3-D integration, Cu/In bonding, interconnect.
I. INTRODUCTION
T
HREE-DIMENSIONAL (3-D) integration can provide a viable solution to allow the extension of Moore’s law and it has also made a significant progress in the develop-ment of electronic products with enhanced performance and functional diversification [1]–[4]. Among the different bonding technologies in 3-D integration, metal-to-metal bonding with good electrical connection and sufficient bonding strength appears to be the mainstream for the development of 3-D interconnects [5].Conventional thermal-compression metal bonding requires high bonding pressure and bonding temperature to achieve high yields [6] that may lead to bonding misalignment and thermal damages of devices. Hence, developing a Manuscript received July 24, 2013; revised October 13, 2013; accepted January 8, 2014. Date of publication February 19, 2014; date of current version March 20, 2014. This work was supported in part by the Ministry of Education in Taiwan under the ATU Program, in part by the Advanced Semiconductor Engineering Group, and in part by the National Science Council under Grant NSC 101-2628-E-009-005 and Grant NSC 102-2221-E-009-160. The review of this paper was arranged by Editor S. Deleonibus.
Y.-S. Chien, Y.-P. Huang, R.-N. Tzeng, C.-T. Chuang, W. Hwang, and K.-N. Chen are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30050, Taiwan (e-mail: [email protected]).
M.-S. Shy, T.-H. Lin, K.-H. Chen, C.-T. Chiu, and H.-M. Tong are with the Advanced Semiconductor Engineering Group, Kaohsiung 81170, Taiwan.
J.-C. Chiou is with the National Chiao Tung University, Hsinchu 300, Taiwan, and also with China Medical University, Taichung 40402, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2304778
low-temperature bonding scheme is significant to meet the low thermal budget requirement [7].
Diffusion soldering has a great potential for the formation of thermally and mechanically stable bonds in electronic applications. Depending on the materials system involved, the bonding process can be performed at low temperature because interconnects consist of intermetallic phases with melting temperature much higher than the fabrication temperature. To achieve this goal, low-melting-point metals, such as In, can be considered as the interconnect material to be bonded during 3-D integration process. After bonding, complete consumption of low-melting-point In is required to avoid reliability issues in the following processes and in future operations.
In a previous work, Tian et al. [8] studied two identical Cu/In interconnects bonded at 260 °C, but only material investigation was reported without any electrical and relia-bility data. Sakuma et al. reported Cu/Ni/In and Cu/Ni/Au bonding results. However, the structure was complicated and no reliability test was evaluated [9]. In this paper, we report a low-temperature (170 °C) Cu/In bonding with an investi-gation on the structural quality, electrical characteristics, and reliability assessment. This bond scheme is simple, using only Cu and In direct bonding. With the obtained excellent bonding results and electrical performance, Cu/In bonding can be recommended as a promising solution for low-temperature bonding.
II. EXPERIMENT ANDINVESTIGATION OF CU/INBONDEDINTERCONNECTS
Copper interconnects for bonding were prepared on silicon wafers with 500-nm TEOS by sputtering 300 nm of Cu and 30 nm of Ti layers in a multitarget chamber with approximate sputtering rates at 0.6 and 0.1 Å/s, respectively. The deposition process was under the working pressure of 7×10−3torr with a base pressure of 1×10−6torr. Indium interconnects for bond-ing were prepared by evaporatbond-ing In and 30 nm of Ti layers with deposition rates at 1.5–1.8 Å/s for In and 1 Å/s for Ti, under a base pressure of 2–4× 10−6 torr. The two different interconnects were then bonded face to face at 1.91 MPa, 170 °C for 30 min. Both chip-to-chip bonding and wafer-to-wafer bonding schemes were performed. The formation of intermetallic phases in the Cu/In bonds, by changing the thick-ness of In, was studied. The bond quality and the materials of 0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
Fig. 1. Structural characteristics of Cu/In bonded interconnect. (a) Cross sectional view of Cu/In bonded structure with the position of EDX spot and (b) corresponding composition with 680-nm thick In layer.
bonded interconnects were analyzed through scanning acoustic tomograph (SAT), transmission electron microscope (TEM), and energy-dispersive X-ray spectrometer (EDX).
The cross sectional views of the Cu/In bonded struc-tures and the composition profiles with different thicknesses (680, 400, 270, and 220 nm) of In are shown in Figs. 1–4. According to EDX analysis, the sample with the largest amount of In shows that Cu and In are uniformly mixed with no apparent IMC phases presented, as shown in Fig. 1. With a smaller amount of In, EDX results in Figs. 2 and 3 show that Cu2In and Cu7In3phases are formed in the structure. For the sample with the least In, no IMC phase is formed in the structure, as shown in Fig. 4.
To explain the inconsistent results for the four cases with different thicknesses of In, the reaction mechanism of Cu/In bonding has been proposed. According to the Cu-In phase diagram, three intermetallic phases can be formed under the bond temperature of 170 °C: Cu11In9, η(Cu2In), and
δ(Cu7In3) [10]. The first IMC of Cu11In9 is formed by the reaction of liquid In and solid Cu. Then, the second Cu-richer IMC of Cu2In starts to form through the interdiffusion between solid Cu and Cu11In9. On heating, the Cu7In3phase with the richest Cu is formed by consumption of Cu2In and Cu [8]–[14].
III. CASESTUDIES
For the case of 680-nm In, as shown in Fig. 1(a) and (b), the absence of IMC is due to excessive In and fast interdiffusion between In and Cu. During the 30-min bonding, with a large
Fig. 2. Structural characteristics of Cu/In bond. (a) Cross sectional view of Cu/In bonded structure with the EDX scanning direction and (b) composition profile obtained by EDX line-scan with 400-nm-thick In layer.
amount of In compared with Cu, the liquid In was not able to fully react with Cu. Therefore, the first IMC of Cu11In9 did not form. Instead, Cu and In were uniformly mixed, which implies that the bonded structure is not preferred and may cause reliability issues.
For the case of 400-nm In, after liquid In reacted with Cu, the first IMC of Cu11In9 was formed. During the 30-min bonding, as the heating process went on, the Cu-richer second IMC of Cu2In started to form by the diffusion of Cu and solid Cu11In9 consumption, as shown in Fig. 2(a) and (b). There was no apparent Cu7In3 detected in this structure owing to the insufficient time for the formation and growth of Cu7In3. Because the growth of Cu2In and Cu7In3 at low temperature requires a large incubation time (longer than 30 min), the reaction was stopped before the appearance of Cu7In3. In addition, no Cu11In9 phase is detected, indicat-ing a complete consumption of Cu11In9 for the formation of Cu2In.
While further decreasing In thickness to 270 nm, the third IMC with richest Cu of Cu7In3 (m.p. 632.2 °C) can be formed by the total consumption of Cu2In and reac-tion with Cu within the 30-min bonding process time. As shown in Fig. 3(a) and (b), there is no In detected in IMC and Cu regions. With the good bonding result of Cu7In3 (m.p. 632.2 °C) formation and the absence of In, the almost defect-free bond structure is preferred for the application of 3-D interconnects.
Fig. 3. Structural characteristics of Cu/In bond. (a) Cross sectional view of Cu/In bonded structure with the EDX scanning direction and (b) composition profile obtained by EDX line-scan with 270-nm-thick In layer.
With the investigation of bond results of 680, 400, and 270 nm In layers, when the thickness of Cu is fixed, the thinner In layer has the better bond quality. However, for the case with thinnest In of 220 nm, the results in Fig. 4(a) and (b) show that Cu atoms have dissolved into liquid In and formed uneven mixture. The final bonded structure should be Cu/Cu7In3in this case based on previous results. To explain this phenomenon, the surface morphologies and roughness of 220-nm In were investigated prior to bonding. As shown in Fig. 5(a) and (b), independent small grains on the substrate are observed, but not a continuous film.
After a small amount of In was deposited on the substrate, separate clusters formed and grew. However, the distance for clusters to coalesce was too high during the deposition process. In addition, according to the previous study [15], due to the enhanced thermal movement and increased atomic diffusivity from the increasing temperature, big clusters of In would split into smaller clusters. Because the surface tension and the viscosity of In are very high at low bonding temperatures, the reaction time for the cluster dispersion should be longer [16]. Therefore, during the bonding process, at a temperature of 170 °C, indium melt required more time to spread over a larger area and uniformly contact with the Cu substrate. However, the reaction had stopped before the occurrence of IMC. Therefore, after 30-min bonding, there is only Cu/In mixed region and unreacted Cu shown in the bonded structure. With the absence
Fig. 4. Structural characteristics of Cu/In bond. (a) Cross sectional view of Cu/In bonded structure with the position of EDX spot and (b) corresponding composition with 220-nm-thick In layer.
Fig. 5. Morphology of dewet In prior to bonding. (a) Top view and (b) cross sectional view.
of IMC, the bonded structure may remelt and cause serious reliability problems during the following process and electrical operation.
Fig. 6. Cu/In wafer bonding result by SAT analysis.
IV. CU/INBONDING FOR3-D INTEGRATION With previous results, owing to its low melting tempera-ture (156.6 °C), In needs to be completely consumed and transferred to intermetallic compounds. The usage amount of In should be kept at minimum. However, when In can-not form a continuous film on substrate, especially under the nanometer scale, the high surface roughness of In will hinder the bonding process and lead to varied formations of intermetallic compounds. Therefore, although thin In layer is preferred for Cu7In3 formation, the In layer is still needed to be thick enough for a continuous film and uniform contact with Cu.
The quality of In layer depends on the thickness, parameters during deposition, and substrate material used. Understanding the morphology of In layer is significant to achieve stable bond structure with the least amount of In usage. If In can be grown into a continuous film on substrate with sufficient amount of Cu for intermetallic compound formation, Cu7In3phase with high thermal stability can be formed and is the best candidate for 3-D integration application.
The SAT analysis of the Cu/In wafer bonding with 270-nm-thick In layer is given in Fig. 6, which demonstrates a uniform wafer-level bonding integrity without voids. Because of its high melting temperature of 632.2 °C, the Cu7In3phase can survive following CMOS and packaging processes. There-fore, this low-temperature Cu-In bond design with Cu/Cu7In3 formation can be applied in 3-D integration, such as the wafer-level lock-n-key scheme. In this scheme, In is designed for the lock structure with its surface lower than dielectric/SiO2 surface, which can prevent In from possible dispersing during the heating process, while Cu is designed for the key structure. As the bonding process proceeds, Cu will diffuse toward In and react to form the final Cu/Cu7In3 bond.
V. ELECTRICALCHARACTERISTIC OF COPPER-/INDIUM-BONDEDINTERCONNECT Specific contact resistance of the Cu-/In-bonded intercon-nect was measured by fabricating a Kelvin structure with the bonded area of 100 μm2 (10 μm × 10 μm) [17]. The measurement result in Fig. 7 suggests a low specific contact resistance of approximately 0.3 × 10−8 -cm2 and a stable
Fig. 7. Measured specific contact resistance of Cu-/In-bonded interconnect under different applied current.
Fig. 8. Electrical characteristic of Cu-/In-bonded interconnect under current stressing test.
bonded structure with a small deviation of resistance under different applied current.
The Cu-/In-bonded interconnect was further evaluated by reliability tests. Fig. 8 also shows the low specific contact resistance after 1000 cycles of current sweeping between
−0.1 and 0.1 A. In addition, it still presents a small deviation
of resistance within the entire 1000 cycles of current sweeping, even at a large current density of 105A/cm2. The good stability of Cu-/In-bonded interconnect against current stressing is especially important for multiple operation and commercial application.
VI. ELECTRICALRELIABILITY OF CU-/IN-BONDEDINTERCONNECT
To evaluate the thermal reliability of Cu-/In-bonded inter-connect, temperature cycling test based on the JESD22-A104B standard was performed under temperature range of −55 to 125 °C with a duration of 15 min/zone [18]. As shown in Fig. 9, the bonded interconnect shows good stability after 1000 loops of temperature cycling, implying that the structure possesses good durability against expansion and shrinkage caused by large temperature variation.
Fig. 9. Reliability test results of Cu-/In-bonded interconnect under temper-ature cycling test.
Fig. 10. Reliability test results of Cu-/In-bonded interconnect under un-biased highly accelerated stress test.
In addition, an unbiased highly accelerated stress test (unbiased HAST) based on the JESD22A-118 standard with the conditions of 85% RH and 130 °C was applied to eval-uate the bonding quality of the interconnect. As shown in Fig. 10, it demonstrates good bonding quality of Cu/In bonded interconnect against moisture and corrosion from the obser-vation of a more stable and lower resistance after 168 h of operation. The reduction of resistance may be attributed to the heat provided by the un-biased HAST that simulates the rearrangement of structures and eliminates the defects at the bonded interface [19].
According to these results, the Cu-/In-bonded interconnect is promising in terms of electrical performance and reliability, and is a possible choice for 3-D integration.
VII. CONCLUSION
In this paper, the scheme of reliable wafer-level and chip-level Cu-/In-bonded interconnects has been proposed and successfully demonstrated at 170 °C low temperature. The detailed study on structural characteristics of intermetallic phases formed in the Cu/In bonds has been presented in
conditions.
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Yu-San Chien received the M.S. degree in
elec-tronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, in 2013.
Yan-Pin Huang received the Degree in material
science engineering from the National Chiao Tung University (NCTU), Hsinchu, Taiwan, where he is currently pursuing the Ph.D. degree in electronics engineering.
Ruoh-Ning Tzeng, photograph and biography not available at the time of
publication.
Ming-Shaw Shy, photograph and biography not available at the time of
publication.
Teu-Hua Lin, photograph and biography not available at the time of
publication.
Kou-Hua Chen, photograph and biography not available at the time of
publication.
Chi-Tsung Chiu, photograph and biography not available at the time of
publication.
Ching-Te Chuang (S’78–M’82–SM’91–F’94) received the Ph.D. degree in electrical engineering from the University of California, Berkeley, CA, USA, in 1982.
He is currently a Life Chair Professor with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan.
Wei Hwang (F’01–LF’09) received the Ph.D. degree
from the University of Manitoba, Winnipeg, MB, Canada.
He is currently a Life Chair Professor of Elec-tronics Engineering with the National Chiao Tung University, Hsinchu, Taiwan.
Jin-Chern Chiou (M’06) received the M.S. and
Ph.D. degrees in aerospace engineering science from the University of Colorado, Boulder, CO, USA, in 1986 and 1990, respectively.
He is currently the Professor of the Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan, and the Department of Medicine, China Medical University, Shenyang, China, the Vice Superintendent/Director of Biomedical Engineering Research and Develop-ment Center, China Medical University Hospital, Taichung, Taiwan.
Ho-Ming Tong (F’07) received the Ph.D. degree
in chemical engineering from Columbia University, New York, NY, USA.
He is currently the Chief Research and Develop-ment Officer and the General Manager of Group Research and Development, ASE Group, Kaohsiung, Taiwan. He served with IBM Thomas J. Watson Research Center, New York, as a Research Staff Member, and as a Senior Engineering Manager with IBM’s East Fishkill Facility.
Kuan-Neng Chen (M’05–SM’11) received the
Ph.D. degree in electrical engineering and computer science, and the M.S. degree in materials science and engineering from the Massachusetts Institute of Technology, Cambridge, MA, USA.
He is currently a Professor with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. He was a Research Staff Member with the IBM Thomas J. Watson Research Center, Yorktown Heights, USA.
