[PDF] Top 20 On-chip ESD protection design by using polysilicon diodes in CMOS process
Has 10000 "On-chip ESD protection design by using polysilicon diodes in CMOS process" found on our website. Below are the top 20 most common "On-chip ESD protection design by using polysilicon diodes in CMOS process".
On-chip ESD protection design by using polysilicon diodes in CMOS process
... of using the bulk p–n junction diodes to realize the bridge rectifying circuit, the on-chip ESD protec- tion circuits for pad1 and pad2 are therefore also realized by the ... See full document
11
Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
... improve ESD robustness of ESD protection devices without sudden degradation as that found in the traditional gate-driven ...power-rail ESD protection circuits have been ... See full document
8
On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... of ESD current involves both avalanche breakdown and turn-on of the parasitic lateral bipolar ...junction in the lateral bipolar ...depends on the relative proximity to the avalanching ... See full document
8
ESD protection design for CMOS RF integrated circuits using polysilicon diodes
... novel ESD protection design with stacked polysilicon diodes for RF ICs has been proposed and ...The polysilicon diode with an un-doped central region can be realized in ... See full document
10
On-chip high-voltage charge pump circuit in standard CMOS processes with polysilicon diodes
... Abstract—An on-chip high-voltage charge pump circuit realized with the polysilicon diodes in standard (bulk) CMOS process is presented in this ...the ... See full document
4
Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
... Abstract—Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated ...drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge ... See full document
8
Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
... of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process Chun-Yu Lin, Member, IEEE, and Mei-Lian Fan Abstract—The pin-to-pin electrostatic ... See full document
10
On-chip transient detection circuit for system-level ESD protection in CMOS ICs
... with ESD voltage of -1500V zapping on the HCP under system-level ESD ...system-level ESD protection has been implemented in a CMOS ...µm process. By ... See full document
4
Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process
... distributed diodes can reduce the ESD-generated heat across each diode, and the ESD robustness can be ...This design can be recognized that at low frequencies, L shorts the input to R T , and ... See full document
7
Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
... for on-chip ESD protection cir- cuits has been successfully investigated in a ...salicided CMOS process. By using the substrate-triggered technique, the ... See full document
9
SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS process
... (MM) ESD robustness of the traditional pMOS-LVTSCR [2] and DHVSCR are measured by a ZapMaster ESD tester, where the devices are in a fully salicided process without using extra ... See full document
3
ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology
... TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, ...boron ESD implantation (Dn with B-imp.). a high operating voltage injecting ESD current through the de- vice, a much larger power is generated at the ... See full document
10
System-level ESD protection design with on-chip transient detection circuit
... new on-chip transient detection circuit for system- level electrostatic discharge (ESD) protection is ...proposed. By including this new proposed on-chip transient ... See full document
4
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
... ESD protection devices cause RF performance degradation with several undesired effects [13], ...the ESD protection device is one of the most important design considerations for RF ... See full document
10
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
... main ESD clamp NMOS transistor to remain at the ON or OFF ...main ESD clamp NMOS transistor has been drawn with the BigFET layout style, which has a minimum drain-contact-to-polygate spacing of ... See full document
5
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
... oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products ...Therefore, on-chip ESD protection circuits must be ... See full document
10
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
... of ESD protection diodes, whole-chip ESD protection scheme can be realized with the active power-rail ESD clamp circuit ...the ESD robustness of the general ... See full document
10
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
... during ESD stresses, a trigger circuit composed of an RC distinguisher and an HV inverter was fabricated on ...the ESD voltage transition is on the order of nanoseconds but normal circuit ... See full document
9
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
... scaled-down CMOS technologies, the power-supply voltages in CMOS ICs have been also scaled downwards to follow the constant-field scaling requirement and to reduce power ...For CMOS IC ... See full document
15
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
... for on-chip ESD protection cir- cuits has been successfully investigated in a ...the ESD pro- tection circuits designed with two DT_SCR devices in stacked configuration ... See full document
11
相關主題