[PDF] Top 20 Design and VLSI implementation of MPEG audio decoder
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Design and VLSI implementation of MPEG audio decoder
... ARCHITECTURE D ESI GN A N D VLSI IMPLEMENTATION Based on our approach for simplicity and low- cost design , dedicated hardware design (ASIC), which offers a more efficient[r] ... See full document
5
Design and VLSI implementation of real-time weighted median filters
... The performance of these sub-optimal weight set for full size Lena image can outperform median filters and center weighted median filters as shown in Table 1.. 3 Propos[r] ... See full document
6
Code design and decoder implementation of low density parity check code
... lot of attention lately due to its excellent error-correcting capability and implementation friendly decoding algorithms ...limit and lower hardware complexity than Turbo codes, LDPC has been ... See full document
3
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters
... distribution, and reproduction in any medium, provided the original work is properly ...values and number representations of digital FIR filters have significant impacts on the complexity of ... See full document
14
VLSI implementation of a modified efficient SPIHT encoder
... fficient VLSI implementation of the modified SPIHT encoder is ...tables and straightforward coding proce- dure are employed. Low-cost and simple hardware imple- mentation is ...The ... See full document
10
Implementation strategy of MPEG-2 audio decoder and efficient multichannel architecture
... In contrast with the pre-processing stage, post-processing stage uses large computation power of whole decoding process with a simple and regular con- trol, and a large am[r] ... See full document
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A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core
... WU AND LIANG-GEE CHEN Department of Electrical Engineering, National Taiwan University, Taiwan, Republic of China Received February 4, 2000; Revised October 16, 2000 ...Abstract. MPEG-2 ... See full document
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A low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder
... This paper presents a low-cost MPEG-2 audio decoder, which is capable of decoding MPEG- 2 standard multichannel audio bitstream for Layer I.. and I1 with a modi:fied decoding sch[r] ... See full document
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VLSI architecture design of MPEG-4 shape coding
... because of the bit-serial processing ...redundancy of data transfer for software ...CAE, and DLM to speedup the performance of computation-extensive ...integrated and scheduled in a ... See full document
11
On the design and implementation of an MPEG-4 scene editor
... The specification of MPEG-4 includes media data access framework, video/audio codec, synthetic object presentation and integration method of different media data.. We[r] ... See full document
2
MPEG-2/4 Low-Complexity Advanced Audio Coding Optimization and Implementation on DSP
... AAC decoder with Odd-time Odd-frequency Discrete Table 9 Tested audio samples with their song length and ...(IMDCT) and optimized inverse quantization ...performance of the proposed AAC ... See full document
13
Design and implementation of an efficient MPEG-4 interactive terminal on embedded devices
... Thc system consists of severill modules: Scene Graph Manager, Media Decoding Framework, Composition Buffer, Audio Engine, and 2D/3D Graphic Engine.. System Architecture.[r] ... See full document
4
A software-hardware co-implementation of MPEG-4 Advanced Video Coding (AVC) decoder with block level pipelining
... idea of MB based loop filtering design is to modify the original frame based loop filtering to fit our design ...memory and no macroblock de- pendency in a frame for deeper ...viewpoint ... See full document
18
A Novel Architecture of Inverse Quantization and Multichannel Processing for MPEG-2 Audio Decoding
... proposed and the other architectures are shown in Table ...VLIW and SIMD, can perform the decoding, they also have disadvantages of a complex circuit design and no optimization in ... See full document
4
Design and implementation of a highly efficient VLSI architecture for discrete wavelet transform
... Compared to the general folded architecture which folds all t h e computatiorls into one filter bank, our folded two- filter-bank architecture can achieve high th[r] ... See full document
4
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
... ACS and ȕ / ACS ...principle of the convolutoinal code is based on the trellis diagram according to the convolutional ...sizes and truth ...length of Viterbi encoder is 9, different from the ... See full document
4
Low power design for MPEG-2 video decoder
... A bus arbitration and scheduling scheme is then proposed to allow larger burst of I/O transfer with less buffer size penalty than the fixed-priority approach Both the Gray[r] ... See full document
9
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
... Therefore, we developed an area-efficient Modified Euclidean architecture, which can reduce the hardware complexity about 50% compared to the fully parallel architec[r] ... See full document
4
A low complexity design of psycho-acoustic model for MPEG-2/4 advanced audio coding
... the MPEG-2/4 AAC ...complexity of AAC encoding ...calculation of spreading ...one-third of the original table ...instead of time domain with the sound quality ...proposed design ... See full document
9
Design and implementation of a bitstream parsing coprocessor for MPEG-4 video system-on-chip solution
... The evaluation result shows the required MOPS of the proposed architecture is only 27 MOPS, which is much lower than that of a general RISC core, while the programmability [r] ... See full document
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