[PDF] Top 20 Design of an Efficient VLSI Architecture for 2-D Discrete Wavelet Transforms
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Design of an Efficient VLSI Architecture for 2-D Discrete Wavelet Transforms
... To explore how our proposed architecture works, we use a computation-schedule table to illustrate three levels of separable 2-D DWT computations for an N x N image a[r] ... See full document
6
Design and implementation of a highly efficient VLSI architecture for discrete wavelet transform
... Compared to the general folded architecture which folds all t h e computatiorls into one filter bank, our folded two- filter-bank architecture can achieve high th[r] ... See full document
4
An efficient VLSI architecture for full-search block matching algorithms
... Instead of local connections of search data flow, we use a global distribution of search data connected to each PE row (or ...Section 2 describes how the general BMA algorithms can be mapped ... See full document
8
Efficient VLSI architecture for 2-D inverse discrete wavelet transforms
... The architecture is designed based on a computation-schedule scheme to process the input signals in real-time, and uses two efficient filter structures to minimize the[r] ... See full document
4
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
... inverses of the lifting coefficients exactly for releasing the timing ...is an integer, can also reduce the critical path, as shown in Fig. 7(d), where the flipping coefficients are and ... See full document
10
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
... use of Verilog-XL and synthesized into gate-level netlists by Synopsys Design Compiler with standard cells from Artisan ...registers. For circuit synthesis, the timing con- straints are set as tight ... See full document
12
An Efficient Architecture for Two-Dimensional Discrete Wavelet Transform
... out of every two samples at the filter output, causing poor hardware ...different design techniques to enhance its ...sum of the odd and even ... See full document
10
An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters
... concept of EIC employs the simply built-in instruction, to command the PALU for the 1-D DWT/IDWT ...1-D architecture is made up of EIC, we put the 2-D DWT into ... See full document
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A Tree-Block Scheduling Architecture for Separable 2-D Inverse Discrete Wavelet Transform
... scheme for 2-D separable IDWT. The advantage of this scheme is that the required buffers stored the temporary subband can be greatly reduced because wavelet coefficients are proc- essed ... See full document
8
Design of an Area-Efficient ASIC Architecture for Context-Based Binary Arithmetic Coding
... employs an adaptive binary arithmetic coder, called MQ ...kind of statistical coding technique, of which the efficiency is better than that of the classical Huffman coding ...probability ... See full document
4
A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec
... Department of Electrical Engineering and Control Engineering, where he currently is ...As an active in- dustry consultant, he is also involved in the chip design and applications of the flash ... See full document
14
An efficient VLSI architecture of 1-D lifting discrete wavelet transform
... Institute of Electronics, Information, and Communication Engineers.. NII-Electronic Library Service..[r] ... See full document
6
A programmable VLSI architecture for 2-D discrete wavelet transform
... In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transfo[r] ... See full document
4
An improved pyramid algorithm for synthesizing 2-D discrete wavelet transforms
... In this paper, we present a new 2-D synthesis PA to improve some defects encountered in the classical PA algorithm that usually requires large latency, long computatio[r] ... See full document
6
An efficient architecture for two-dimensional discrete wavelet transform
... The advantages of the proposed architecture are the near 100% hardware utilization, fast computation time, regular data flow, and low complexity control circuit, making this desi[r] ... See full document
4
VLSI architecture for discrete wavelet transform based on B-spline factorization
... Two polyphase decomposition types The main advantage of the B-spline factorized architec- tures is that possibly fewer multipliers are required than the convolution and lif[r] ... See full document
5
An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000
... pipelined architecture for the lifting-based 2-D DWT of the 9/7 filter defined in JPEG ...path of 1-D architecture can be shortened by using less pipeline registers ... See full document
9
Hardware-efficient architecture design of wavelet-based adaptive visible watermarking
... based visible watermarking to solve this problem. Wavelet- based visible watermarking is applied to JPEG-2000 image and many consumer electronics product. These technique[r] ... See full document
5
Reconfigurable discrete wavelet transform architecture for advanced multimedia systems
... The lifting-based reconfigurable processing element array possesses better computational efficiency than convolution-based architecture, and a systematic de- sign method[r] ... See full document
5
Lifting based discrete wavelet transform architecture for JPEG2000
... Multiplication is realized in hard\+ ired multiplier with coefficients represented i n canonic signcd-digit (CSD) form. It is a compact and efficient DWT core for the [r] ... See full document
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