[PDF] Top 20 Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
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Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
... (TSMC) and National Science Council (NSC), Tai- wan, under Contract NSC ...meetings of TSMC during circuit de- sign and measurement on the ESD protection cells, where the par- ticipants ... See full document
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ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
... ESD protection devices cause RF performance degradation with several undesired effects [13], ...tance of the ESD protection device is one of the most important ... See full document
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Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
... Abstract—Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated ...oxide and silicided drain/source in nanoscale CMOS technologies seriously ... See full document
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Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
... Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process Chun-Yu Lin, Member, IEEE, and Mei-Lian ... See full document
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Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process
... the ESD-generated heat across each diode, and the ESD robustness can be ...capacitances of D P1 –D N1 pair, D P2 –D N2 pair and high-speed circuits, and D P3 –D N3 pair ... See full document
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ESD protection design for CMOS RF integrated circuits using polysilicon diodes
... Conclusion A novel ESD protection design with stacked polysilicon diodes for RF ICs has been proposed and ...realized in general sub-quarter- micron CMOS ... See full document
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Self-Matched ESD Cell in CMOS Technology for 60-GHz Broadband RF Applications
... The ESD cells for 60-GHz broadband RF applications are presented in this ...These ESD cells have reached the 50-Ω input/output matching. This ESD cell ... See full document
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Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
... new ESD protection circuit with low parasitic capaci- tance, large swing tolerance, high ESD robustness, and good latchup immunity has been developed for the gigahertz power ...test ... See full document
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Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
... impedance-isolation ESD protection design with LC- tank (called as the LCD ...Dimensions of inductors and capacitors used in ...product of inductance and ... See full document
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Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits
... novel ESD protection cell for 24-/60-GHz dual-band applications has been designed, fabricated, and characterized in a 65-nm CMOS ...test ... See full document
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ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
... TRINGS A. Conventional Diode String in CMOS Technology The cross-sectional view of the conventional four-stage diode string is shown in ...Because of the parasitic vertical p-n-p ... See full document
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Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
... robustness and parasitic capacitance. After determining the dimen- sions of ESD protection diodes, whole-chip ESD protection scheme can be realized with the active power-rail ... See full document
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ESD protection design for 1-to 10-GHz distributed amplifier in CMOS technology
... difference of the time delay over the 16-GHz bandwidth was controlled to the ...The in- ductor model can be adjusted by changing the turns. The DA is kept in optimization cycles until these ... See full document
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A 3-10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits
... proposed ESD-protected UWB LNA is designed and fabricated using 130 nm CMOS ...technology. A source-follower output buffer and is integrated in the LNA for the ... See full document
3
On-chip ESD protection design by using polysilicon diodes in CMOS process
... was a Visiting Associate Professor in the Department of Electrical Engineering, Portland State University, Portland, ...been a Professor with the National Chiao-Tung University, where he is ... See full document
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On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... drain of the top nMOS and the source of the bottom ...emitter and collector, respectively. Their spacing determines the base width and turn-on efficiency of the lateral bipolar ... See full document
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Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
... analysis and experimental results, the substrate-triggered technique has been confirmed to contin- ually improve ESD robustness of ESD protection devices without sudden degradation as ... See full document
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ESD protection design to overcome internal damage on interface circuits,of a CMOS IC with multiple separated power pins
... II. ESD F AILURE IN CMOS IC W ITH M ULTIPLE S EPARATED P OWER P INS A clock generator IC had been fabricated in a ...m CMOS process and used to supply 11 ... See full document
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Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
... studied in this work, the heavily doped PBI layer reduces the effective resistance of p-body ...the of nLDMOS is increased, because the turn-on operation of the BJT requires , where is the ... See full document
9
A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process
... Two ESD protection schemes for a 5-GHz differential LNA have been verified in a 130-nm CMOS ...Both ESD pro- tection schemes have the same parasitic ... See full document
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