[PDF] Top 20 New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
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New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
... uniformity of the SCR device under ESD stress, the failure analyses were carried out by scanning electron microscopy ...the ESD failure locations on the 2 × VDD-tolerant ... See full document
5
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
... Taiwan, in 1993. He has been the Department Manager of the VLSI Design Division, Computer and Communication Re- search Laboratories, Industrial Technology Research Institute, ...Department ... See full document
6
New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
... with I-Shou University, Kaohsiung, ...Department of Electronics Engineering, Na- tional Chiao Tung University, and also the Executive Director with the National Science and Technology Program on ... See full document
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Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
... A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only IxVDD devices for 3xVDD-tolerant mixed-voltage [r] ... See full document
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Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... on ESD protection designs for the mixed-voltage I/O circuits without suffering the gate-oxide reliability ...improve ESD level of the mixed-voltage ... See full document
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ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
... Manager in the VLSI Design Division of the Computer and Communica- tion Research Laboratories (CCL), Industrial Tech- nology Research Institute (ITRI), ...Professor in the Department of ... See full document
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ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
... major ESD current will be discharged through the path (path C) is that the negative ESD current is discharged through the parasitic diode of nMOS (Mn) to VSS, and then through the embedded SCR ... See full document
10
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
... The ESD clamp circuit with SCR widths of 45 m, 60 m, and 90 m can achieve It2 of ...trigger voltage of the SCR device is as high as ...shown in Fig. 8. ... See full document
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The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
... holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply ...danger in the practical system ... See full document
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Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
... proposed power-rail ESD clamp circuit has been de- signed and fabricated in a 130-nm ...fabricated in the same chip for reference. In the test ... See full document
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Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
... × VDD-tolerant power-rail ESD clamp circuits operates without gate-oxide reliability issue under the normal circuit operating ...control circuit in the 3 × ... See full document
10
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
... Discussion In general, the normal VDD power-on voltage waveform has a rise time on the order of milliseconds and an amplitude of VDD operation ...amplitude in ... See full document
5
Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
... Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology Chih-Ting Yeh, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE ... See full document
8
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
... capacitance of different metal-layer capaci- tors, the test devices of MIM and MOM capacitors had been fabri- cated in the silicon chip with a 65 nm CMOS ...process. In ... See full document
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Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology
... quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC ...member of Technical Program Committees and the Session ... See full document
9
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
... A new ESD protection design, using the stacked-nMOS trig- gered silicon controlled rectifier (SNTSCR) device, has been successfully verified in a ...m CMOS process. The – ... See full document
10
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
... the voltage of node A is ...the voltage of node B low enough to turn on the pMOS transistor due to the voltage drop on the resistor ...loop of the ESD-transient detection ... See full document
11
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
... The new ESD protection circuit with low parasitic capaci- tance, large swing tolerance, high ESD robustness, and good latchup immunity has been developed for the gigahertz power ... See full document
8
On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
... the ESD-transient detection circuit is added with diode string to adjust its holding ...the ESD clamp nMOS transistor is drawn in BigFET layout style without silicide blocking, large ... See full document
9
Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
... VLSI Design Division, Computer, and Communication Re- search Laboratories, Industrial Technology Research Institute, ...Department of Electronics En- gineering, National Chiao Tung University, where ... See full document
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