[PDF] Top 20 An efficient pipeline architecture for deblocking filter in H.264/AVC
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An efficient pipeline architecture for deblocking filter in H.264/AVC
... the H.264/AVC deblocking filter is mainly based on two ...scribed in the previous section, the computation of boundary strength, the threshold value of Alpha and Beta, the table- ... See full document
9
An in-place architecture for the deblocking filter in H.264/AVC
... boundaries for (a) luma data, and (b) chroma ...Overall architecture. than a whole MB bits as in the conventional data ...described in the brief, in general, requires all MB data to be ... See full document
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Architecture design for deblocking filter in H.264/JVT/AVC
... Our basic idea is to buffer the 8x4 unfilteredlfiltered pixels of two adjacent 4x4-blocks in an 8x4 pixel array with reconfigurable data path in order to support both hori- zont[r] ... See full document
4
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
... encoder for real- time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential al- gorithms in ...loops. In this paper, we ... See full document
16
An in/post-loop deblocking filter with hybrid filtering schedule
... made in Section ...of deblocking filters in different stan- dards, we tabulate each feature in Table ...boundaries. In general, most of deblocking filters obey an order ... See full document
7
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding
... System Architecture A decoder architecture can be obtained by mapping the blocks in the decoding paths in ...characteristics. For example, the syntax parser is characterized with a lot ... See full document
15
A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder
... bin in a SE may be binIdx − plus1 (binIdx + 1) or binIdx − plus2 (binIdx + ...calculated in parallel. In the end the value of current SE is confirmed, the CABAC decoder can keep processing without ... See full document
10
Hardware architecture design of an H.264/AVC video codec
... methodology for H.264/AVC video codec. The system architecture and scheduling will be ...optimization for its significant modules including bandwidth optimized motion compen- ... See full document
8
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture
... As for EC/DB stage, modification of algorithm will influence the consistence between encoder and ...MB pipeline problem caused by data dependencies with left MB does not ex- ...demanded for DB to be ... See full document
4
An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000
... Conclusion In this paper, we propose a high-speed and low-memory pipelined architecture for the lifting-based 2-D DWT of the 9/7 filter defined in JPEG ...1-D architecture can be ... See full document
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Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
... of an H.264/AVC decoder is the system architecture design with balanced pipelining schedules and proper degrees of ...parallelism. In this paper, a hybrid task pipelining scheme ... See full document
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A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC
... developed an optimized MPEG-2 software encoder. For his work in the encoder and MPEG-4 areas, he received two Sarnoff achievement awards and three Sarnoff team ...participated in ISO's Moving ... See full document
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An Efficient Mode Preselection Algorithm for Fractional Motion Estimation in H.264/AVC Scalable Video Extension
... standard, H.264/AVC scalable video extension (SVC), adopts various advanced interlayer pre- diction modes to explore the data redundancies between layers for better coding efficiency but at ... See full document
12
Hardware architecture design for H.264/AVC intra frame coder
... ABSTRACT In this paper, we contributed a VLSI architecture design for ...system architecture achieves 215 times of speed compared with RISC-based software implementation in terms of ... See full document
4
Exploiting fine-grain parallelism in the H.264 deblocking filter by operation reordering
... opportunities for parallelization. In H.264, the standard defined orders intersect with each other on a 4 × 4 grid; thus, we used four-pixel-long boundaries as the basic ...unit. In the ... See full document
12
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
... Manufactured in The United States Abstract The H.264/AVC Fractional Motion Estima- tion (FME) with rate-distortion constrained mode decision can improve the rate-distortion efficiency by 2–6 ... See full document
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Projection based adaptive window size selection for efficient motion estimation in H.264/AVC
... quality for a given bit rate, because it may select long mo- tion vectors that need many bits to transmit it also does not help determining how the subdivision should be performed, because the smallest blocks will ... See full document
7
An efficient matrix-based DCT splitter/merger for MPEG-2-to-AVC/H.264 transform kernel conversion
... An Efficient Matrix-Based DCT Splitter/Merger for ...Abstract—An efficient matrix-based discrete cosine transform splitter/merger for realizing MPEG-2 to ...presented in ... See full document
6
An Improved Detection Method for Z Q ti d Bl k H 264/AVC Zero Quantized Blocks on H.264/AVC
... An Improved Detection Method for Z Q ti d Bl k H 264/AVC Zero Quantized Blocks on H.264/AVC.. Bo-Jhih Chen and Shen-Chuan Tai.[r] ... See full document
19
Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC
... parallelized for sequential manner of half and quarter re- finement ...suitable for parallelism because interpolated pixels can be reused for adjacent candidates of each sub-block, and redun- dant ... See full document
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