[PDF] Top 20 ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
Has 10000 "ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process" found on our website. Below are the top 20 most common "ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process".
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
... ESD protection devices cause RF performance degradation with several undesired effects [13], ...the ESD protection device is one of the most important design considerations ... See full document
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Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits
... novel ESD protection cell for 24-/60-GHz dual-band applications has been designed, fabricated, and characterized in a 65-nm CMOS ...24 GHz (60 ... See full document
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Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
... of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process Chun-Yu Lin, Member, IEEE, and Mei-Lian Fan ... See full document
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Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
... oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products ...on-chip ESD protection circuits must be added at all input/output ... See full document
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Initial-on ESD protection design with PMOS-triggered SCR device
... novel SCR design with “initial-on” function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD ...any ... See full document
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Latchup-free ESD protection design with complementary substrate-triggered SCR devices
... R.O.C., in 1986, 1988, and 1993, respectively. In 1994, he joined the VLSI Design Department of Computer and Communication Research Labora- tories (CCL), Industrial Technology Research Insti- tute ... See full document
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Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process
... NANSCR WITH FASTER TURN-ON SPEED FOR ESD PROTECTION IN A ...0.13-µm CMOS PROCESS 553 same and equal to ∼ 16 (∼ 1) V/µm 2 ...be triggered on in ...lateral ... See full document
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Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
... Abstract—Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated ...drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge ... See full document
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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
... used for on-chip ESD protection cir- cuits has been successfully investigated in a ...salicided CMOS process. By using the substrate-triggered technique, the STSCR device ... See full document
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SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
... used for on-chip ESD protection cir- cuits has been successfully investigated in a ...salicided CMOS process. With both the substrate and n-well triggered currents, ... See full document
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Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology
... Lecturer in IEEE Circuits and Systems Society for ...Taiwan ESD Association in ...Foundation. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by ... See full document
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ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
... shown in Fig. 14. The It2 of the input pad under PS-mode ESD stress with silicide blocking on pMOS and nMOS devices is 3 A, and that without silicide blocking is 2 ...embedded SCR structures ... See full document
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On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... stacked-nMOS for conducting large amounts of ESD current involves both avalanche breakdown and turn-on of the parasitic lateral bipolar ...junction in the lateral bipolar ...increase in the ... See full document
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Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
... improve ESD robustness of ESD protection devices without sudden degradation as that found in the traditional gate-driven ...design. With the substrate-triggered technique, ... See full document
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Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
... of ESD protection diodes, whole-chip ESD protection scheme can be realized with the active power-rail ESD clamp circuit ...the ESD robustness of the general receiver and ... See full document
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ESD protection design for 1-to 10-GHz distributed amplifier in CMOS technology
... The in- ductor model can be adjusted by changing the turns. The DA is kept in optimization cycles until these goals can not be ap- ...structure with the component values is shown in ... See full document
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Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
... Taiwan. In the field of reliability and quality design for circuits and systems in CMOS technology, he has published over 360 technical papers in international journals and ... See full document
7
SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology
... STSCR with (b) STI and (c) dummy-gate structures under different substrate-triggered ...during ESD-zapping conditions. With the suitable ESD-detection circuit, the STSCR with ... See full document
8
ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
... improve ESD robustness of stacked-nMOS devices in mixed-voltage I/O circuits, a new ESD protection design has been proposed and successfully verified in a ...m CMOS ... See full document
10
Self-Matched ESD Cell in CMOS Technology for 60-GHz Broadband RF Applications
... cells with 1-stage ESD protection. The 1-stage ESD protection is designed with a low-C pad, an on-chip spiral inductor, and a pair of ESD ...cells with ... See full document
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