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[PDF] Top 20 A hierarchical N-queen decimation lattice and hardware architecture for motion estimation

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A hierarchical N-queen decimation lattice and hardware architecture for motion estimation

A hierarchical N-queen decimation lattice and hardware architecture for motion estimation

... A Hierarchical N-Queen Decimation Lattice and Hardware Architecture for Motion Estimation Chung-Neng Wang, Member, IEEE, Shin-Wei Yang, ... See full document

12

Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile

Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile

... factors, and m 1 , m 3 are rotation factors, and m 2 , m 5 are translation ...has a large computation complexity, but also needs a very large memory bandwidth because of many iterations of ... See full document

4

Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264

Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264

... HARDWARE ARCHITECTURE DESIGN FOR VARIABLE BLOCK SIZE MOTION ESTIMATION IN MPEG-4 AVC/JVT/ITU-T H.264.. Yu- Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, and Liang-Gee Chen DSPlIC Design L[r] ... See full document

4

Analysis and Hardware Architecture Design of Global Motion Estimation

Analysis and Hardware Architecture Design of Global Motion Estimation

... bandwidth and 80% iterations can be ...interpolation and differential values, and it can also reduce the cycles of memory ...techniques, a hardware architecture for GME in ... See full document

16

Analysis and hardware architecture for global motion estimation in MPEG-4 Advanced Simple Profile

Analysis and hardware architecture for global motion estimation in MPEG-4 Advanced Simple Profile

... GME in MPEG-4 ASP is analyzed, and a hardware- oriented GME algorithm is proposed according to the analysis re- sults, which is a combination of a feature points based algor[r] ... See full document

4

Efficient hierarchical motion estimation algorithm and its VLSI architecture

Efficient hierarchical motion estimation algorithm and its VLSI architecture

... ( for respectively). MRMC-m is a MMEA based on multiple candidates, and it has m-candi- dates at each ...1, and two of the MV candidates that are obtained on the basis of minimum matching ... See full document

14

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

... second and 3.8 tera bytes per second in D1 Format and dominated by IME, which is estimated by instruction profiling of reference software, ...[20] and the simulation environment is P4-1.8 GHz ... See full document

16

Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder

Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder

... 2. Architecture mapping: Based on the analysis of [22], the basic hardware architecture of FME engine is shown in ...VBS, and the SATD computation is also based on 4  4 ...Therefore, a ... See full document

17

A hierarchical decimation lattice based on N-queen with an application for motion estimation

A hierarchical decimation lattice based on N-queen with an application for motion estimation

... Terms—Fast motion search, -queen lattice, pixel deci- ...block motion estimation as the most computation- ally intensive ...improve motion estimation by reducing the ... See full document

4

A novel all-binary motion estimation (ABME) with optimized hardware architectures

A novel all-binary motion estimation (ABME) with optimized hardware architectures

... filtering, decimation, binarization, and ...filters and integrate several steps into a unified process by removing the redundant ...complexity, and thus the power consumption for ... See full document

13

Combinative motion estimation algorithm and the corresponding architecture for complex motion phenomenon

Combinative motion estimation algorithm and the corresponding architecture for complex motion phenomenon

... dx and dy. Add motion vector dx and dy to the estimated complex motion parameters. After proposed the combinative algorithm, the performance comparison of the propose[r] ... See full document

9

A content-based methodology for power-aware motion estimation architecture

A content-based methodology for power-aware motion estimation architecture

... Methodology for Power-Aware Motion Estimation Architecture Hsien-Wen Cheng and Lan-Rong Dung, Member, IEEE Abstract—This paper presents a novel power-aware motion ... See full document

5

Global elimination algorithm and architecture design for fast block matching motion estimation

Global elimination algorithm and architecture design for fast block matching motion estimation

... GEA and its architecture design for fast block matching ...block, and then to precisely compare the best roughly matched candidate blocks with cur- rent ...fixed, and the ... See full document

10

Parallel global elimination algorithm and architecture design for fast block matching motion estimation

Parallel global elimination algorithm and architecture design for fast block matching motion estimation

... presents a new parallel global elimination algorithm and architecture for fast block ...distortion estimation, only a few most probable candidates are required to determine the ... See full document

4

MOTION RESTORATION - A METHOD FOR OBJECT AND GLOBAL MOTION ESTIMATION

MOTION RESTORATION - A METHOD FOR OBJECT AND GLOBAL MOTION ESTIMATION

... an arbitrary object are first processed for zooming estimation which extracts the zoom vector V from the motion vector V. The difference vector 1/,. The two estimation sub-steps may 1)e [r] ... See full document

12

The Optimal Design for Motion Estimation Algorithm on Cell Processor Architecture

The Optimal Design for Motion Estimation Algorithm on Cell Processor Architecture

... (二) 以 8 顆 SPE 平行運算進行加速 我們使用 8 顆 SPE 平行運算的方式與前面 提到那篇的做法不同,他的方法是將每張參考 影像放在不同的 SPE 裡面運算,而我們的做法 則是將原本的影像拆成八分,如圖 5.(a);與一 顆 SPE 計算一張影像比較,拿 8 顆 SPE 把一張 影像平分的作法在 DMA 傳輸的資料量就有差 別了,在一顆算一張影像的情況下,每顆 SPE 必須取得 2 ... See full document

12

Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC

Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC

... frame and ignore the first ...positions, and ultra random access of search window(SW) memory is required if this loop is ...parallelized for sequential manner of half and quarter re- finement ... See full document

4

An efficient binary motion estimation algorithm and its architecture for MPEG-4 shape encoding

An efficient binary motion estimation algorithm and its architecture for MPEG-4 shape encoding

... is a software approach. Thus, our proposed algo- rithm is suitable for software and hardware ...implementation. For hardware design comparison, the proposed algorithm is simple ... See full document

10

A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video

A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video

... two hardware design techniques to solve these problems men- tioned ...of a low cycle count, which is crucial to HD ...levels for data reuse ...range for the most frequently occurring ...Thus, ... See full document

10

A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding

A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding

... Terms—H.264/AVC, motion estimation, video coding. I. I NTRODUCTION I N RECENT years, multimedia application has become more flexible and powerful with the development of semiconduc- tors, ... See full document

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