[PDF] Top 20 ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
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ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
... the mixed-voltage I/O buffers with or without the proposed substrate-triggered ...not triggered by such a voltage ...0–8-V voltage pulse is applied to ... See full document
10
On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... (ESD), ESD protection circuit, mixed-voltage I/O circuits, substrate-triggered ...technique. I. I NTRODUCTION T O IMPROVE ... See full document
8
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
... normal circuit operating condition, the substrate-trig- gered circuit can meet the gate-oxide reliability constraints and the local substrate of the stacked nMOS is biased at VSS by the ... See full document
12
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... the substrate-triggered stacked- NMOS device are shown in ...the substrate-triggered ...the substrate-triggered ...equivalent substrate resistance (R sub ) for ... See full document
9
ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
... VLSI Design Division of the Computer and Communica- tion Research Laboratories (CCL), Industrial Tech- nology Research Institute (ITRI), ...quality design for circuits and systems in CMOS technology, ... See full document
8
Substrate-triggered ESD protection circuit without extra process modification
... high ESD protection level, a robust field-oxide device (FOD) is often used as the main discharge element in the primary protection stage to discharge ESD ...limit ESD current flowing ... See full document
8
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
... new ESD protection design, using the stacked-nMOS trig- gered silicon controlled rectifier (SNTSCR) device, has been successfully verified in a ...device with different gate biases and the ... See full document
10
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
... VLSI Design Department of Computer and Communication Research Labora- tories (CCL), Industrial Technology Research Insti- tute (ITRI), Taiwan, as a Circuit Design ...VLSI Design Division of ... See full document
13
ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS
... process. With the single-finger layout style, HBM ESD levels of the LVTp-n-p devices in the ...VSS ESD-stress conditions. Moreover, HBM ESD levels of the LVTp-n-p devices in the ... See full document
11
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
... the voltage of node A is ...the voltage of node B low enough to turn on the pMOS transistor due to the voltage drop on the resistor ...the ESD-transient detection circuit is started ... See full document
11
Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection
... Staff with AT&T Bell Laboratories, Holmdel, ...Professor with the Department of Electrical and Computer Engineering, University of Illinois, ...Professor with Katholieke Universiteit, Leuven, ... See full document
5
Design of mixed-voltage I/O buffer by using NMOS-blocking technique
... quality design for nanoelectronics and gigascale systems, high-speed or mixed-voltage I/O interface circuits, special sensor circuits, and thin-film transistor (TFT) ...quality ... See full document
10
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
... stacked-NMOS triggered silicon-controlled recti- fier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ... See full document
3
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
... [13] ESD event before the breakdown on the ESD protection devices, a 5-V voltage pulse with a rise time of 10 ns is applied to ...transient voltage waveforms and the triggering ... See full document
5
Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
... power-rail ESD clamp circuits operates without gate-oxide reliability issue under the normal circuit operating ...control circuit in the 3 × VDD-tolerant ESD clamp circuit B, the device ... See full document
10
Initial-on ESD protection design with PMOS-triggered SCR device
... Arrangements for On-Chip Applications The on-chip ESD protection designs for input, output, and power-rail ESD clamp circuits with PMOS-triggered SCR devices and the ... See full document
4
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
... major ESD current will be discharged through the path (path C) is that the negative ESD current is discharged through the parasitic diode of nMOS (Mn) to VSS, and then through the embedded SCR structure ... See full document
10
Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
... the circuit analysis and experimental results, the substrate-triggered technique has been confirmed to contin- ually improve ESD robustness of ESD protection devices without ... See full document
8
System-level ESD protection design with on-chip transient detection circuit
... co-design ESD protection function, a hardware/firmware system co- design combined the transient detection circuit and the power-on reset circuit has been ...power-on ... See full document
4
Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit
... derived design model to find suitable layout parameters for minimizing the input capacitance variation can help the analog ESD protection circuit to be well realized in general CMOS ... See full document
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