[PDF] Top 20 On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
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On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... stacked-nMOS for conducting large amounts of ESD current involves both avalanche breakdown and turn-on of the parasitic lateral bipolar ...effective substrate resistance ( ) to ground, may ... See full document
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ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
... VLSI Design Department, Computer and Communication Research Labo- ratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan, ...R.O.C. In 1998, he was the Department Manager of the VLSI ... See full document
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Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
... the substrate-triggered technique has been confirmed to contin- ually improve ESD robustness of ESD protection devices without sudden degradation as that found in the ... See full document
8
ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
... new ESD protection scheme with an ESD_BUS and a high- voltage-tolerant ESD clamp circuit for a SoC with ...V mixed-voltage I/O ... See full document
8
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... overview on ESD protection designs for the mixed-voltage I/O circuits without suffering the gate-oxide reliability ...improve ESD level of the ... See full document
9
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
... Discharge Protection Design for Mixed-Voltage CMOS I/O Buffers Ming-Dou Ker, Senior Member, IEEE, and Chien-Hui Chuang Abstract—A new electrostatic discharge ... See full document
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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
... used for on-chip ESD protection cir- cuits has been successfully investigated in a ...salicided CMOS process. By using the substrate-triggered ... See full document
9
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
... used for on-chip ESD protection cir- cuits has been successfully investigated in a ...salicided CMOS process. With both the substrate and n-well ... See full document
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On-chip ESD protection design by using polysilicon diodes in CMOS process
... Professor with the National Chiao-Tung ...Professor in the Department of Electrical Engineering, Portland State University, Portland, ...Professor with the National Chiao-Tung University, where he is ... See full document
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Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
... R.O.C., in 1993. He was the Department Man- ager with the VLSI Design Division, Com- puter and Communication Research Laborato- ries, Industrial Technology Research Institute, ...sor ... See full document
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Substrate-triggered ESD protection circuit without extra process modification
... of ESD protection circuits is seriously degraded by the advanced CMOS fabrication technologies, especially when the lightly doped drain (LDD) structure and silicided diffusion are used ...and ... See full document
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Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
... of ESD protection diodes, whole-chip ESD protection scheme can be realized with the active power-rail ESD clamp circuit ...the ESD robustness of the general ... See full document
10
ESD protection design for CMOS RF integrated circuits using polysilicon diodes
... novel ESD protection design with stacked polysilicon diodes for RF ICs has been proposed and ...diode with an un-doped central region can be realized in general ... See full document
10
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
... R.O.C., in 1986, 1988, and 1993, respectively. In 1994, he joined the VLSI Design Department of Computer and Communication Research Labora- tories (CCL), Industrial Technology Research Insti- ... See full document
13
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
... the substrate-triggered technique. The ESD discharging paths of the new proposed I/O cells with embedded SCR structures under ESD stresses have been clearly ... See full document
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Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
... of I-Shou University, Kaohsiung, Taiwan. In the field of reliability and quality design for circuits and systems in CMOS technology, he has published over 360 technical ... See full document
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Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
... investigated in a 0.6-lm CMOS process. By using the substrate-triggered technique, the DTDB, STDB, and STLB devices can provide much higher ESD ro- bustness within a ... See full document
14
Initial-on ESD protection design with PMOS-triggered SCR device
... “initial-on” ESD protection concept by using the PMOS-triggered SCR device with RC-based ESD detection circuit has been successfully designed and verified in a ... See full document
4
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
... gate-coupled technique with consideration of the gate-oxide reliability issue, is used to provide suitable gate bias to trigger on the SNTSCR device under ESD stress ...condition. On ... See full document
12
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
... ESD protection devices cause RF performance degradation with several undesired effects [13], ...the ESD protection device is one of the most important design considerations ... See full document
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