[PDF] Top 20 High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
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High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
... Manager with the VLSI Design Division, Computer and Communication Re- search Laboratories, Industrial Technology Research Institute, ...Professor with the Institute of Electronics Engineer- ing, National ... See full document
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Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
... MOSFET in sub-threshold region, one mod- ified design with the additional timer level restorer was reported in ...pulled high by the turned-on PMOS M1. However, with a leaky gate MOS ... See full document
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Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
... A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only IxVDD devices for 3xVDD-tolerant mixed-voltage [r] ... See full document
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Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
... AIL ESD C LAMP C IRCUIT A. Circuit Schematic The new proposed power-rail ESD clamp circuits of the ultralow standby leakage are shown in ...tively, with p- and ... See full document
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New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
... President with I-Shou University, Kaohsiung, ...Professor with the Department of Electronics Engineering, Na- tional Chiao Tung University, and also the Executive Director with the National Science ... See full document
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Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
... of ESD detection circuit under 0-to-6 V ESD-like transition on ESD bus line (the line for node e overlaps with the line for node ...VDD-Tolerant ESD Clamp Circuits ... See full document
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ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
... new ESD protection scheme with an ESD_BUS and a high- voltage-tolerant ESD clamp circuit for a SoC with ...verified in a 0.13-µm CMOS ... See full document
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Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
... shown in Table 4. However, with the different refer- ence frequencies in the measurement, the capacitance variations of two capacitors are quite ...summarized in Table 5. As shown in ... See full document
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Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... on ESD protection designs for the mixed-voltage I/O circuits without suffering the gate-oxide reliability ...improve ESD level of the mixed-voltage I/O circuits, the ESD protection ... See full document
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Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
... Professor with the Department of Electronics Engi- neering, National Chiao Tung ...program with the College of Electrical Engi- neering and Computer Science, National Chiao Tung University, as well as the ... See full document
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On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
... oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection ...power-rail ESD clamp circuit has been the key ... See full document
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Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
... Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology Chih-Ting Yeh, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE Abstract—A resistor-less power-rail electrostatic ... See full document
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High Area-Efficient ESD Clamp Circuit With Equivalent RC-Based Detection Mechanism in a 65-nm CMOS Process
... power-rail ESD clamp circuit, a TLP voltage pulse with a rise time of 2 ns and a pulse height of 4 V is applied to the VDD power line with the VSS ...TLP voltage pulse can ... See full document
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The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
... holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply ...danger in the practical system applications, ... See full document
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New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
... (ESD) clamp circuit realized with only thin gate oxide 1-V (1 × VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified ... See full document
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Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
... V in the 3-V ...overshooting voltage pulse on the VDD power line. The ESD clamp circuit for placing between the VDD and VSS power lines should be verified in such a condition to ... See full document
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Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
... as high as two to three times the supply voltage ...SCR ESD protection designs with a diode from output pad to limits the maximum signal swing at RF ...large-swing-tolerant ESD ... See full document
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Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
... power-rail ESD clamp circuit has been de- signed and fabricated in a 130-nm ...1-V/2.5-V CMOS process. The stand-alone STnMOS with the same device dimension and layout has ... See full document
7
Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
... gate-tunneling leakage of the MOS capacitor on the circuit performance in the second-order PLL has been analyzed and investigated in a 90-nm 1-V CMOS ...gate-tunneling leakage of ... See full document
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ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
... string with four stacked diodes in CMOS ...BJTs in a triple-well CMOS process. ESD clamp circuits, the sizes of ESD-protection devices at the RF input node ... See full document
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