1.2.1. System-Level ESD Tests
The equivalent circuit of ESD gun used in the system-level ESD test is shown in Fig. 1.1 The ESD gun has the charging (energy-storage) capacitor of 150 pF and discharge resistor of 330 Ω. The equivalent circuit of human body model (HBM) in the component-level ESD test
is shown in Fig. 1.2 In the HBM component-level ESD test, however, the charging capacitor (discharge resistor) is a smaller (larger) value of 100pF (1.5 kΩ). Thus, compared with the ESD current in component-level ESD test, ESD current in system-level ESD test has a much larger peak current and a shorter rise time, leading to more severe damages for electronic products or their interior ICs. The ESD-induced energy can be zapped out of the mechanism with ESD gun in faster speed.
Fig. 1.1 Equivalent circuit of ESD gun used in the system-level ESD test. The ESD gun has the charging (energy-storage) capacitor of 150 pF and discharge resistor of 330 Ω.
Fig. 1.2 Equivalent circuit of human body model (HBM) in the component-level ESD test.
The charging capacitor (discharge resistor) is a smaller (larger) value of 100 pF (1.5 kΩ).
Fig. 1.3 shows the typical waveforms of the discharge current under system-level ESD test (IEC 61000-4-2) and component-level ESD test (MIL-STD 883). Under 8-kV ESD zapping, the peak current in system-level ESD test is about five times larger than that in component-level ESD test. Additionally, ESD protection designs for system- and component-
level ESD tests are quite different. It has been proven [10] that a robust CMOS IC product with high component-level ESD levels could be very susceptible to the system-level ESD test.
Thus, efficient ESD protection methodologies against system-level ESD events are very significant for electronic products.
Fig. 1.3 Under 8-kV ESD zapping, the peak current in system-level ESD test is about five times larger than that in component-level ESD test.
In the IEC 61000-4-2 standard [9], two test modes have been specified, which are the air-discharge test mode and the contact-discharge test mode. Contact discharge is further divided into direct discharge to the system under test, and indirect discharge to horizontal or vertical coupling planes. Fig. 1.4 shows the standard measurement setup of the system-level ESD test in the indirect contact-discharge test mode. As shown in Fig. 1.5, in the air discharge test mode, the round discharge head of ESD gun is brought close to the EUT. In the contact discharge test mode, the sharp discharge head of ESD gun is held in contact with the EUT. The measurement setup for system-level ESD test consists of a wooden table on the grounded reference plane (GRP). In addition, an insulation plane is used to separate the EUT from the horizontal coupling plane (HCP). The HCP are connected to the GRP with two 470 kΩ resistors in series. When the ESD gun zaps the HCP, the electromagnetic interference (EMI) coming from ESD will be coupled into all CMOS ICs inside EUT. The power lines of CMOS ICs inside EUT will be disturbed by the ESD-coupled energy.
Fig. 1.4 Measurement instruments of system-level ESD test [9].
Fig. 1.5 Discharge electrodes of ESD gun which is used under system-level ESD test with contact discharge mode and air discharge mode.
The object of the standard, IEC 61000-4-2 is to establish a common and reproducible basis for evaluating the performance of CMOS ICs inside the electrical/electronic microelectronic products. This standard specifies typical waveform of the discharge current, test levels, test equipment, test set-up, and test procedure. In order to verity the disturbance under system-level ESD test, the ESD gun is used to zap the ESD-induced energy into the equipment under test. In order to compare the test results in system-level ESD and component-level ESD standards, the characteristics of the waveform of discharge current are shown in Table 1.1. Table 1.2 shows the test level (test voltage) of component-level ESD test
such as human body model (HBM), machine model (MM), and charge device model (CDM) in usual condition. The system-level ESD test level with contact discharge and air discharge is shown in Table 1.3. Contact discharge is the preferred test method, and air discharge shall be used where contact discharge can’t be applied. It is not intended to imply that the test severity is equivalent between contact discharge and air discharge test methods. To compare Table 1.3 with Table 1.2, the test voltage of system-level ESD is lager than component-level ESD, no matter with contact discharge or air discharge. Noteworthiness, the voltages shown are different for each method due to the different methods of test. According to those phenomena, system-level ESD is more significant to influence the microelectronic products than component-level ESD in some situations. Table 1.4 shows the evaluation of test results, the test results shall be classified in terms of loss function or degradation of performance of the equipment under test. Generally speaking, the microelectronic product should reset itself automatically after system-level ESD test to pass the “Class B” specification at least. The equipment under test shall be operated within the specified climatic conditions to avoid unnecessary electromagnetic environment of the laboratory influencing the test results.
Table 1.1
Waveform Parameters of System-Level ESD Discharge Current
Table 1.2
Component-Level ESD Specifications
Table 1.3
Levels of System-Level ESD Test
Table 1.4
Recommended Classifications of System-Level ESD Test Results
To evaluate the performance of electrical/electronic equipments subjected to electromagnetic compatibility (EMC) regulation, performing the system-level ESD tests for the electrical/electronic equipments is necessary. The inset figure in Fig. 1.6 shows an EUT (keyboard) which was stressed by an ESD gun with a charged voltage of +1 kV zapping on the horizontal coupling plane (HCP). During the system-level ESD test, the power and ground lines of the microcontroller IC in the keyboard no longer maintain their normal voltage levels, but an underdamped sinusoidal voltage with the amplitude of several hundred volts occurred, as shown in Fig. 1.6 This ESD-generated transient is quite large and fast, which can randomly couple to the power, ground, or I/O pins of microelectronics system.
Such a high-voltage-level fast transient causes the keyboard to be upset or frozen after the
system-level ESD zapping. Such fast electrical transients can also cause transient-induced latchup events in CMOS ICs [26]-[28].
Fig. 1.6 Measured VDD and VSS waveforms of the microcontroller ICs inside the keyboard with ESD voltage of +1 kV zapping on the HCP under system-level ESD test [10].
This ESD-generated transient voltage is quite large (with the amplitude of several tens to hundreds volts) and fast (with the period of several tens nanoseconds) and randomly exists on power, ground, or I/O pins of the ICs inside the microelectronic system. Such a high-voltage-level ESD-induced fast transients often cause the CMOS ICs inside the EUT to be upset or frozen after the system-level ESD zapping. It has been reported that, for a capacitive fingerprint sensor circuit, the MOSFET devices can be melted from device surface into silicon substrate under system-level ESD test with air discharge mode. It has been also observed that, under system-level ESD tests, the underdamped sinusoidal voltage waveforms coupled on VDD and VSS pins of a super twisted nematic (STN) LCD driver circuit can cause abnormal display function of LCD panel. Such a high-energy ESD-induced fast transients can cause serious reliability events on CMOS ICs inside the microelectronic products. Therefore, the CMOS ICs inside the microelectronic products are very susceptible to system-level ESD stress, even though they have passed the component-level ESD specifications such as human-body-model (HBM) of ±2 kV, machine-model (MM) of ±200 V, and charged-device-model (CDM) of ±1 kV.
1.2.2. Electrical Fast Transient (EFT) Tests
The standard of IEC 61000-4-4 defines immunity requirements and test methods for electronic equipment to repetitive fast transients [29]. The EFT is a test with repetitive burst string consisting of a number of fast pulses, coupled into power supply, control, signal, and ground ports of microelectronic products. The characteristics of EFT are high amplitude, short rise time, and high repetition rate of the transients. The EFT test is intended to demonstrate the immunity of microelectronic products to transient disturbances such as those originating from switching transients (interruption of inductive loads, relay contact bounce, etc.).
According to the standard of IEC 61000-4-4, the simplified circuit diagram of EFT generator is shown in Fig. 1.7 with the impedance matching resistor Rm of 50 Ω and the dc blocking capacitor Cd of 10 nF. The charging capacitor Cc is used to store the charging energy and Rc is the charging resistor. The resistor Rs is used to shape the pulse duration. The parameters of EFT generator is summarized in Table 1.5.
Fig. 1.7 The equivalent circuit of EFT generator.
Table 1.5
Characteristics of the EFT Generator
The standard of IEC 61000-4-4 defines the test voltage waveforms of these fast transients with the repetition frequency of 5 kHz and 100 kHz. The use of 5 kHz repetition rate is the traditional EFT test and 100 kHz is closer to reality. For EFT pulse with the repetition frequency of 5 kHz, there are totally 75 pulses in each burst string and the burst duration time is 15ms. For EFT pulse with the repetition frequency of 100 kHz, there are 75 pulses in each burst string and the burst duration time is only 0.75 ms. For both repetition rates, the burst string repeats every 300 ms. The characteristics of EFT burst are summarized in Table 1.6.
For EFT pulses with the repetition frequency of 5 kHz, the measured +200-V and -200-V voltage waveforms on the 1-kΩ load are shown in Figs. 1.8(a) and 1.8(b), respectively.
Because the output loading (1 kΩ) is larger than the impedance matching resistor Rm (50 Ω), the measured output pulse peak is close to the input EFT voltage pulse. As shown in Figs.
1.8(a) and 1.8(b), the measured output pulse peaks on the 1-kΩ load are approximately +200 V and -200 V, respectively. For EFT repetition frequency of 5 kHz, the time interval between each pulse is 0.2ms. Under EFT tests, the application time should not be less than 1 minute and both polarities have to be tested. With the 1 kΩ load, the voltage waveforms of a single pulse with EFT voltage of +200 V and -200 V are shown in Figs. 1.9(a) and 1.9(b), respectively. In Figs. 1.9(a) and 1.9(b), the waveforms of a single pulse have a rise time of
∼5ns and the pulse duration (time interval at half of peak EFT voltage) of ∼50 ns. The characteristics of a single EFT pulse are summarized in Table 1.7.
Table 1.6
Characteristics of the Fast Transient/Burst
Table 1.7
Characteristics of a Single EFT Voltage Pulse
(a)
(b)
Fig. 1.8 Measured voltage waveforms under EFT tests with EFT voltage of (a) +200 V, and (b) -200 V, on 1-kΩ load with a repetition rate of 5 kHz.
(a)
(b)
Fig. 1.9 Measured voltage waveforms of a single pulse with EFT voltage of (a) +200 V, and (b) -200 V, on 1-kΩ load under EFT test.
The EFT levels for testing power supply ports and for testing I/O, data, and control ports of the equipment are listed in Table 1.8. The voltage peak for testing I/O, data, and control ports is half of the voltage peak for testing power supply ports. The repetition rate is determined by specific products or product types. Level “X” is an open level, which is specified in the dedicated equipment specification by customers. The output voltage peaks of EFT test are listed in Table 1.9. With output load of 50 Ω, the measured output voltage is 0.5 times the value of open-circuit load due to impedance matching.
Table 1.8 Levels of EFT Test
Table 1.9
Output Voltage Peak (VP) Values and Repetition Rates under EFT Test