Transient-Induced Latchup in CMOS Integrated Circuits under EFT Tests
5.3. HSPICE Simulation Results
5.3.1. System-Level ESD Zapping Conditions
From the measured electrical transient waveforms shown in Fig. 1.6, the underdamped sinusoidal voltage waveform on power line of CMOS ICduring the system-level ESD stress has been observed. There, a sinusoidal time-dependent voltage source with damping factor parameter given by
( )= 0+ a⋅sin(2π ( − d)) exp( (⋅ − − d) a)
V t V V f t t t t D (1)
is used to simulate an underdamped sinusoidal voltage on the power lines of the new proposed on-chip transient detection circuit II. With the proper parameters (including the applied voltage amplitude Va, initial dc voltage V0, damping factor Da, frequency f, and time delay td), the underdamped sinusoidal voltage can be used to simulate the electrical transient waveforms under system-level ESD tests. In HSPICE simulation with positive-going or negative-going underdamped sinusoidal waveforms, the same parameters of Da = 2x107 s-1, f
= 50 MHz, and td = 300 ns are used (which is corresponding to the measured transient waveforms in Fig. 1.6). For the positive-going (negative-going) underdamped sinusoidal waveform, the polarity of Va parameter is positive (negative). In addition, V0 is 1.8 V as the initial dc voltage on the VDD line of the new proposed on-chip transient detection circuit II this work, which is fabricated in a 0.18-μm CMOS process.
The simulated VDD and VOUT waveforms of the new proposed on-chip transient detection circuit II with a positive-going underdamped sinusoidal voltage on VDD line are shown in Fig.
5.2(a). The positive-going underdamped sinusoidal voltage with amplitude of +10 V is used to simulate the coupling ESD transient noise under the system-level ESD test. From the simulated waveforms, VDD begins to increase rapidly from 1.8 V and VOUT also acts with a positive-going underdamped sinusoidal voltage waveform during the simulated transient disturbance on VDD line. After this disturbance duration, VDD returns to its normal voltage level of 1.8 V and the output state (VOUT) of the new proposed on-chip transient detection circuit II is changed from 0 V to 1.8 V, as shown in Fig. 5.2(a). As a result, the new proposed on-chip transient detection circuit II can detect the occurrence of positive-going ESD-induced underdamped sinusoidal transient disturbance on VDD line.
The simulated VDD and VOUT waveforms of the new proposed on-chip transient detection circuit II with a negative-going underdamped sinusoidal voltage on VDD are shown in Fig.
5.2(b). The negative-going underdamped sinusoidal voltage with amplitude of -10 V is used to simulate the coupling ESD transient noise under the system-level ESD test with negative voltage. From the simulated waveforms, VDD begins to decrease rapidly from 1.8 V and VOUT
also acts with a negative-going underdamped sinusoidal voltage waveform during the simulated transient disturbance on VDD line. After this disturbance duration, VDD returns to its normal voltage level of 1.8 V and the output state (VOUT) of the new proposed on-chip transient detection circuit II is changed from 0 V to 1.8 V, as shown in Fig. 5.2(b). Therefore, the new proposed on-chip transient detection circuit II can detect the occurrence of negative-going ESD-induced underdamped sinusoidal transient disturbance on VDD line.
(a)
(b)
Fig. 5.2 Simulated VDD and VOUT waveforms of the transient detection circuit II under system-level ESD test with (a) positive, and (b) negative underdamped sinusoidal voltages.
From aforementioned simulation results, the output state of the new proposed on-chip transient detection circuit II can be changed and kept at 1.8 V after the system-level ESD events. Therefore, the new proposed transient detection circuit can memorize the occurrence of system-level ESD events.
5.3.2. EFT Zapping Conditions
For microelectronic products, the shielding plate is often designed into microelectronic products to bypass or reduce the EFT-induced electrical transient disturbance. Therefore, the electrical transients injected into CMOS ICs inside the microelectronic products can be degraded with smaller amplitude compared with the original testing voltage. Therefore, the EFT-induced transients with different degraded amplitudes are taken into considerations in HSPICE simulation on the new proposed on-chip transient detection circuit II.
From the measured electrical transient waveforms shown in Figs. 5.3(a) and 5.3(b), the approximated exponential voltage pulse waveforms during the EFT tests have been observed.
There, an exponential pulse time-dependent voltage source with rise/fall time constant parameters is used to simulate EFT-induced transient disturbance on the new proposed on-chip transient detection circuit II. The rising edge of this exponential time-dependent voltage pulse is expressed as
(
2)
The falling edge of this exponential time-dependent voltage pulse is expressed as
(
2) (
1)
With the proper parameters (including the rise time constant τ1, fall time constant τ2, rise time delay td1, fall time delay td2, initial dc voltage value V1, and exponential pulse voltage value V2), the exponential voltage pulse can be constructed to simulate the EFT-induced disturbance under EFT tests. In HSPICE simulation with positive or negative exponential voltage pulse waveforms, the same parameters of τ1 = 3 ns, τ2 = 25 ns, and td2 - td1 = 10 ns are used (which is corresponding to the measured transient waveforms in Figs. 1.9(a) and 1.9(b)). For the
positive exponential voltage pulse, the value of V2 parameter is larger than the value of V1
parameter. For the negative exponential voltage pulse, the polarity of V2 - V1 parameter is negative. In addition, V1 is 1.8 V as the initial dc voltage on the VDD line of the new proposed on-chip transient detection circuit II.
The simulated VDD and VOUT waveforms of the new proposed on-chip transient detection circuit II with a positive and negative exponential pulse transient disturbance on VDD line are shown in Fig. 5.3(a) and 5.3(b), respectively.
(a)
(b)
Fig. 5.3 Simulated VDD and VOUT waveforms of the new proposed on-chip transient detection circuit II under EFT tests with (a) positive, and (b) negative exponential voltage pulse waveforms coupled to VDD.
The simulated VDD and VOUT waveforms of the new proposed on-chip transient detection circuit II with a positive exponential pulse transient disturbance on VDD line are shown in Fig.
5.3(a). The exponential voltage pulse with amplitude of +10 V is used to simulate the coupling positive transient disturbance under the EFT test. From the simulated waveforms, VDD begins to increase rapidly from 1.8 V and VOUT also acts with a positive exponential voltage pulse waveform during the simulated transient disturbance on VDD line. After the transient disturbance duration, VDD returns to its normal voltage level of 1.8 V and the output state (VOUT) of the new proposed on-chip transient detection circuit II transits from 0 V to 1.8 V, as shown in Fig. 5.3(a). As a result, the new proposed on-chip transient detection circuit II can detect the occurrence of simulated positive EFT-induced exponential pulse transient disturbance.
The simulated VDD and VOUT waveforms of the new proposed on-chip transient detection circuit II with a negative exponential pulse transient disturbance on VDD line are shown in Fig.
5.3(b). The exponential voltage pulse with amplitude of -10 V is used to simulate the coupling negative transient disturbance under the EFT test. From the simulated waveforms, VDD begins to decrease rapidly from 1.8 V and VOUT also acts with a negative exponential voltage pulse during the simulated transient disturbance on VDD line. After the transient disturbance duration, VDD returns to its normal voltage level of 1.8 V and the output state (VOUT) of the new proposed on-chip transient detection circuit II transits from 0 V to 1.8 V, as shown in Fig. 5.3(b). As a result, the new proposed on-chip transient detection circuit II can detect the occurrence of simulated negative EFT-induced exponential pulse transient disturbance.
From the aforementioned simulation results, after the positive or negative EFT-induced transient disturbance on VDD line, the output state of the new proposed on-chip transient detection circuit II can be changed from 0 V and kept at 1.8 V. Therefore, the new proposed on-chip transient detection circuit II can successfully memorize the occurrence of simulated positive or negative EFT-induced exponential pulse transient disturbance.
The new proposed on-chip transient detection circuit II has been designed and fabricated in a 0.18-μm 1P5M CMOS process. The fabricated chip for transient disturbance tests is shown in Fig. 5.4. The TLU measurement method, the system-level ESD gun, and the EFT generator are used to evaluate the detection function of the new proposed on-chip transient detection circuit II after EFT-induced electrical transient disturbance.
Fig. 5.4 Die photo of the new proposed on-chip transient detection circuit II.
5.4. Experimental Results
5.4.1. TLU Tests
In the TLU measurement setup shown in Fig. 5.5, a charging capacitance of 200pF is used to store charges offered by the TLU-triggering source, VCharge, and then these stored charges are discharged to the device under test (DUT) through the relay. The intended underdamped sinusoidal voltage can be produced to simulate the transient voltage on the power pins of CMOS ICs under the system-level ESD test, no matter which polarity (positive or negative) the ESD voltage is. Moreover, a small current-limiting resistance of 5Ω is recommended to protect the DUT from electrical-over-stress (EOS) damage during a high-current (low-impedance) latchup state. The supply voltage of 1.8 V is used as VDD and the trigger source is directly connected to DUT through the relay in the measurement setup.
Fig. 5.5 Measurement setup for transient-induced latchup (TLU).
Figs. 5.6(a) and 5.6(b) show the measured VDD and VOUT transient responses of the new proposed on-chip transient detection circuit II under the TLU test with VCharge of +8 V and -1 V, respectively.
(a)
(b)
Fig. 5.6 Measured VDD and VOUT waveforms on the new proposed on-chip transient detection circuit II under TLU tests with VCharge of (a) +8 V, and (b) -1 V.
As shown in Fig. 5.6(a), under the TLU test with VCharge of +8 V, VDD begins to increase rapidly from 1.8 V and acts like positive-going underdamped sinusoidal voltage waveform.
During the TLU test, VOUT is influenced simultaneously with positive-going underdamped sinusoidal voltage coupled to VDD power line. After the TLU test with the VCharge of +8 V, the output voltage (VOUT) of the new proposed on-chip transient detection circuit II can transit
from 0 V to 1.8 V. As shown in Fig. 5.6(b), under the TLU test with VCharge of -1 V, VDD
begins to decrease rapidly from 1.8V and acts like negative-going underdamped sinusoidal voltage waveform. During the TLU test, VOUT is influenced simultaneously with negative-going underdamped sinusoidal voltage coupled to VDD power line. After the TLU test with the VCharge of -1 V, the output voltage (VOUT) of the new proposed on-chip transient detection circuit II can transit from 0 V to 1.8 V.
From the TLU test results, the new proposed on-chip transient detection circuit II can successfully memorize the occurrence of electrical transients. With positive or negative underdamped sinusoidal voltages coupled to VDD power line, the output voltages (VOUT) of the new proposed on-chip transient detection circuit II can be changed from 0V to 1.8V after TLU tests.
5.4.2. System-level ESD Tests
Fig. 5.7 shows the standard measurement setup of the system-level ESD test with indirect contact-discharge test mode. The measurement setup of system-level ESD test consists of a wooden table on the grounded reference plane (GRP). In addition, an insulation plane is used to separate the EUT from the horizontal coupling plane (HCP). The HCP are connected to the GRP with two 470 kΩ resistors in series. When the ESD gun zaps the HCP, the electromagnetic interference (EMI) coming from ESD gun will be coupled into all CMOS ICs inside EUT. The power lines of CMOS ICs inside EUT will be disturbed by the ESD-coupled energy.
Fig. 5.7 Measurement setup for system-level ESD test with indirect contact-discharge test mode to evaluate the detection function of the fabricated on-chip transient detection circuit II.
Figs. 5.8(a) and 5.8(b) show the measured VDD and VOUT transient responses of the new proposed on-chip transient detection circuit II under system-level ESD test with the ESD voltage of +0.2 kV and -0.2 kV zapping on the HCP, respectively.
(a)
(b)
Fig. 5.8 Measured VDD and VOUT transient voltage waveforms of the new proposed on-chip transient detection circuit II under system-level ESD tests with ESD voltage of (a) +0.2 kV, and (b) -0.2 kV.
The measured VDD and VOUT waveforms of the new proposed on-chip transient detection circuit II under system-level ESD test with the ESD voltage of +0.2 kV zapping on the HCP are shown in Fig. 5.8(a). VDD begins to increase rapidly from the normal voltage of +1.8 V.
Meanwhile, VOUT is disturbed under such a high-energy ESD stress. During the period with positive-going ESD-induced electrical transient disturbance, VDD and VOUT are influenced simultaneously. Finally, the output voltage (VOUT) of the new proposed on-chip transient detection circuit II transits from 0 V to 1.8 V. Therefore, the new proposed on-chip transient detection circuit II can sense the positive-going electrical transient on the power line and memorize the occurrence of system-level ESD event.
The measured VDD and VOUT transient voltage waveforms of the new proposed on-chip transient detection circuit II with the ESD voltage of -0.2 kV zapping on the HCP under system-level ESD test are shown in Fig. 5.8(b). During the negative-going ESD-induced electrical transient disturbance on VDD power line, VOUT is disturbed simultaneously. After the system-level ESD test with the ESD voltage of -0.2 kV, VOUT transits from 0 V to 1.8 V.
From the experimental results, the new proposed on-chip transient detection circuit II can indeed detect and memorize the occurrence of positive or negative electrical transients after system-level ESD tests.
5.4.3. EFT Tests
5.4.3.1. With Attenuation Network
The measurement setup for EFT test combined with attenuation network is shown in Fig.
5.9. A supply voltage of 1.8 V is used as VDD and EFT generator is connected to the DUT through the attenuation network. The VDD and VOUT transient responses of the new proposed on-chip transient detection circuit II are monitored by the digital oscilloscope.
Fig. 5.9 Measurement setup for EFT test combined with attenuation network.
Figs. 5.10(a) and 5.10(b) show the measured VDD and VOUT transient responses of the new proposed on-chip transient detection circuit II under the EFT tests with input EFT voltages of +200 V and -300 V, respectively.
(a)
(b)
Fig. 5.10 Measured VDD and VOUT waveforms on the new proposed on-chip transient detection circuit II under EFT tests with (a) positive, and (b) negative EFT voltages combined with attenuation network.
As shown in Fig. 5.10(a), under the EFT test with input EFT voltage of +200 V, VDD
begins to increase rapidly from 1.8 V and acts like positive exponential voltage pulse. During the EFT test, VOUT is influenced simultaneously with positive exponential voltage pulse
coupled to VDD power line. After the EFT test with the input EFT voltage of +200 V, the output voltage (VOUT) of the new proposed on-chip transient detection circuit II transits from 0 V to 1.8 V. As shown in Fig. 5.10(b), under the EFT test with input EFT voltage of -300 V, VDD begins to decrease rapidly from 1.8 V and acts like negative exponential voltage pulse.
During the EFT test, VOUT is influenced simultaneously with negative exponential voltage pulse coupled to VDD power line. After the EFT test with the input EFT voltage of -300 V, the output voltage (VOUT) of the new proposed on-chip transient detection circuit II transits from 0 V to 1.8 V.
From the EFT test results shown in Figs. 5.10(a) and 5.10(b), with positive or negative exponential voltage pulses coupled to VDD power line, the output voltages (VOUT) of the new proposed on-chip transient detection circuit can be changed from 0 V to 1.8 V. Therefore, the new proposed on-chip transient detection circuit II can successfully memorize the occurrence of EFT-induced exponential pulse transient disturbance.
5.4.3.2. With Capacitance Coupling Clamp
The measurement setup for EFT test combined with capacitive coupling clamp is shown in Fig. 5.11. A supply voltage of 1.8V is used as VDD and the capacitive coupling clamp is connected with EFT generator to directly couple the EFT testing voltages into the VDD cable line. The VDD and VOUT voltage waveforms of the new proposed on-chip transient detection circuit II are monitored by the digital oscilloscope during the EFT tests. With such a measurement setup, the circuit function of the new proposed on-chip transient detection circuit II under EFT tests combined with capacitive coupling clamp can be evaluated.
Fig. 5.11 Measurement setup for EFT test combined with capacitive coupling clamp.
Figs. 5.12(a) and 5.12(b) show the measured VDD and VOUT transient responses of the new proposed on-chip transient detection circuit II under the EFT test with input EFT voltages of +200 V and -200 V, respectively.
(a)
(b)
Fig. 5.12 Measured VDD and VOUT transient voltage waveforms of the new proposed on-chip transient detection circuit II under EFT tests with EFT voltage of (a) +200 V, and (b) -200 V combined with capacitive coupling clamp.
As shown in Fig. 5.12(a), under the EFT tests with input EFT voltage of +200 V, VDD
begins to increase rapidly from 1.8V and acts like positive-going underdamped sinusoidal
voltage waveform. During the EFT test, VOUT is influenced simultaneously with positive-going underdamped sinusoidal voltage coupled to VDD power line. After the EFT test with the input EFT voltage of +200 V, the output voltage (VOUT) of the new proposed on-chip transient detection circuit II transits from 0 V to 1.8 V. As shown in Fig. 5.12(b), under the EFT test with EFT voltage of -200 V, VDD begins to decrease rapidly from 1.8 V and acts like negative-going underdamped sinusoidal voltage waveform. During the EFT test, VOUT is influenced simultaneously with negative-going underdamped sinusoidal voltage coupled to VDD power line. After the EFT test with the input EFT voltage of -200 V, the output voltage (VOUT) of the new proposed on-chip transient detection circuit II transits from 0 V to 1.8 V.
From the EFT test results shown in Fig. 5.12(a) and 5.12(b), with positive-going or negative-going underdamped sinusoidal voltage waveforms coupled to VDD power line, the output voltages (VOUT) of the new proposed on-chip transient detection circuit II can be changed from 0 V to the voltage level of 1.8 V. Therefore, the new proposed on-chip transient detection circuit II can successfully memorize the occurrence of positive-going or negative-going EFT-induced underdamped sinusoidal transient disturbance.
5.5. Conclusion
A new on-chip transient detection circuit II has been proposed and successfully verified in a 0.18-μm CMOS process. The detection function under different positive or negative ESD-induced and EFT-induced electrical transient disturbance has been investigated by HSPICE simulation. The experimental results have verified that the new proposed on-chip transient detection circuit II can detect and memorize the occurrence of electrical transients under system-level ESD or EFT testing conditions. With hardware/firmware co-design, the new proposed on-chip transient detection circuit II can be further used as firmware index to provide an effective solution against the malfunction in microelectronic products caused by ESD-induced and EFT-induced electrical transient disturbance.
Chapter 6
On-Chip Transient-to-Digital Converter
A novel on-chip transient-to-digital converter composed of four transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18-μm complementary-metal-oxide-semiconductor (CMOS) process with 3.3-V devices.
The output digital thermometer codes of the proposed on-chip transient-to-digital converter correspond to different electrical transient voltages under system-level ESD and EFT tests.
These output digital codes can be used as the firmware index to execute different auto-recovery procedures in microelectronic systems. Thus, the proposed on-chip transient-to-digital converter can be further combined with firmware design to provide an
These output digital codes can be used as the firmware index to execute different auto-recovery procedures in microelectronic systems. Thus, the proposed on-chip transient-to-digital converter can be further combined with firmware design to provide an