System-Level ESD Test

In the standard of IEC 61000-4-2, two test modes have been specified, which are air-discharge test mode and contact-discharge test mode. Fig. 2.8 shows the standard measurement setup of the system-level ESD test with indirect contact-discharge test mode.

The measurement setup of system-level ESD test consists of a wooden table on the grounded reference plane (GRP). In addition, an insulation plane is used to separate the equipment under test (EUT) from the horizontal coupling plane (HCP). The HCP are connected to the GRP with two 470 kΩ resistors in series. When the ESD gun zaps the HCP, the electromagnetic interference (EMI) coming from the ESD will be coupled into all CMOS ICs inside EUT. The power lines of CMOS ICs inside EUT will be disturbed by such high ESD-coupled energy.

Compared with the component-level HBM ESD tests, where the objects under test are ICs, the system-level ESD test aims to evaluate the robustness of electronic products. The equivalent circuit of ESD gun used in the system-level ESD test. The ESD gun has the charging (energy-storage) capacitor of 150pF and discharge resistor of 330Ω. In the HBM component-level ESD test, however, the charging capacitor (discharge resistor) is a smaller (larger) value of 100pF (1.5kΩ). Thus, compared with the ESD current in component-level ESD test, ESD current in system-level ESD test has much larger peak current and shorter rise time, leading to more severe damages for electronic products or their interior ICs. It has also been proven that a robust CMOS IC product with high component-level ESD levels could be very susceptible to the system-level ESD test. Thus, efficient ESD protection methodologies against system-level ESD events are very significant for electronic products.

Fig. 2.8 Measurement setup for system-level ESD test with indirect contact-discharge mode.

With such a standard measurement setup, the susceptibility of different power-rail ESD clamp circuits against the system-level ESD stresses can be evaluated. The stand alone power-rail ESD clamp circuit in IC package is powered up with power supply of 1.8 V.

Before any ESD zapping, the initial VDD voltage level on the IC is measured to make sure the correct bias of 1.8 V. After every ESD zapping, the voltage level on VDD node of IC is measured again to watch whether latchup-like failure occurs after the system-level ESD test, or not. If the latchup-like failure occurs, the potential on VDD node will be pulled down to a much lower level due to the latch-on state of ESD-clamping NMOS in the power-rail ESD clamp circuits, and IDD will be significantly increased.

With the system-level ESD measurement setup in Fig. 2.8, the VDD and IDD transient responses can be recorded by the oscilloscope, which can clearly indicate whether the latchup-like failure occurs or not. Figs. 2.9(a) and 2.9(b) show the measured VDD and IDD

transient responses on the power-rail ESD clamp circuit with typical RC-based detection when ESD gun with ESD voltage of -10 kV and +10 kV zapping on the HCP, respectively.

After the system-level ESD test with an ESD voltage of -10 kV, latchup-like failure is not initiated in this power-rail ESD clamp circuit, because IDD is still kept at zero, as shown in Fig. 2.9(a). After the system-level ESD test with an ESD voltage of +10 kV, latchup-like failure is not observed in Fig. 2.9(b). Under system-level ESD test with ESD voltage of -10 kV and +10 kV, the measured VDD and IDD transient waveforms on the power-rail ESD clamp circuit with PMOS feedback are shown in Figs. 10(a) and 10(b), respectively. Under system-level ESD test with an ESD voltage of -10 kV (+10 kV), VDD acts with the intended

bipolar trigger. Meanwhile, latchup-like failure does not occur because IDD is not increased, as shown in Fig. 2.10(a) (Fig. 2.10(b)). For the power-rail ESD clamp circuits with typical RC-based detection or PMOS feedback, latchup-like failure does not occur even though the ESD voltage is as high as -10 kV or +10 kV in the system-level ESD test.

(a)

(b)

Fig. 2.9 Measured VDD and IDD waveforms on the power-rail ESD clamp circuit with typical RC-based detection under system-level ESD test with ESD voltage of (a) -10 kV, and (b) +10 kV.

(a)

(b)

Fig. 2.10 Measured VDD and IDD waveforms on the power-rail ESD clamp circuit with PMOS feedback under system-level ESD test with ESD voltage of (a) -10 kV, and (b) +10 kV.

Figs. 2.11(a) and 2.11(b) show the measured VDD and IDD transient responses on the power-rail ESD clamp circuit with NMOS+PMOS feedback under the system-level ESD test with ESD voltages of -0.2 kV and +2.5 kV, respectively. After the system-level ESD test with

an ESD voltage of -0.2 kV, latchup-like failure can be initiated in this power-rail ESD clamp circuit, because IDD is significantly increased and VDD is pulled down as shown in Fig. 2.11(a).

After the system-level ESD test with an ESD voltage of +2.5 kV, the latchup-like failure can be also found in Fig. 2.11(b).

(a)

(b)

Fig. 2.11 Measured VDD and IDD waveforms on the power-rail ESD clamp circuit with NMOS+PMOS feedback under system-level ESD test with ESD voltage of (a) -0.2 kV, and (b) +2.5 kV.

For the power-rail ESD clamp circuit with cascaded PMOS feedback, the measured VDD

and IDD transient responses are shown in Figs. 2.12(a) and 2.12(b) under the system-level ESD test with ESD voltages of -1 kV and +10 kV, respectively. The similar latchup-like failure also occurs due to the latch-on state of ESD-clamping NMOS under the system-level ESD test with an ESD voltage of -1 kV, as shown in Fig. 2.12(a).

(a)

(b)

Fig. 2.12 Measured VDD and IDD waveforms on the power-rail ESD clamp circuit with cascaded PMOS feedback under system-level ESD test with ESD voltage of (a) -1 kV, and (b) +10 kV.

The susceptibility among the aforementioned four different power-rail ESD clamp circuits against system-level ESD test are listed in Table 2.2. The power-rail ESD clamp circuits with NMOS+PMOS feedback or with cascaded PMOS feedback have lower ESD voltages to cause latchup-like failure after system-level ESD test. Such measured results by ESD gun test are consistent with those of TLU shown in Table 2.1. From the experimental results, the power-rail ESD clamp circuit designed with NMOS+PMOS feedback is highly sensitive to transient-induced latchup-like failure. The typical power-rail ESD clamp circuits with RC-based detection and with PMOS feedback are free to such a latchup-like failure.

Table 2.2

Comparison on the Susceptibility among Four Different Power-Rail ESD Clamp Circuits Under System-Level ESD Test

The failure location after system-level ESD test has been inspected, as shown in Fig.

2.13. The failure location is located at the VDD metal line from the VDD pad to the power-rail ESD clamp circuit, which was drawn with a metal width of 30 μm in the test chip.

Fig. 2.13 Failure location of power-rail ESD clamp circuit after system-level ESD stress.