Transient-Induced Latchup in CMOS Integrated Circuits under EFT Tests
4.5. Hardware/Firmware Co-design Application
The proposed transient detection circuit can be co-designed with firmware to provide a system solution to solve the system-level ESD issue of microelectronic products realized with CMOS ICs. It has been proven that the hardware/firmware can be co-designed can be used to effectively improve the system-level ESD robustness of the CMOS IC products.
As shown in the flowchart in the Fig. 4.20, the detection results (VOUT) from the on-chip transient detection circuits can be temporarily stored as a firmware index for system check. The output states of the transient detection circuit I and the firmware index are initially cleared to logic 0 by the power-on reset circuit. The reset procedure is executed through the normal firmware reset procedure when the firmware index has a state of logic 0. When the fast electrical transient happens, the on-chip transient detection circuit can detect the fast electrical transient to change the output states from logic 0 to logic 1. At the same time, the firmware index is re-stored at logic 1, and the system executes the recover procedure to recover all system functions to a stable state as soon as possible. After recover procedures, the output state of the proposed on-chip transient detection circuit I and the firmware index are re-set to logic 0 again for detecting the next ESD and EFT events.
Fig. 4.20 The hardware/firmware co-design flowchart to execute reset or recover procedures.
For example, to realize system-level ESD protection function, a hardware/firmware co-design solution combined with the transient detection circuit and the power-on reset circuit has been analyzed. Under the normal power-on condition, the VDD power-on voltage waveform has a rise time in the order of millisecond (ms). As there is no input signal except VDD power-on voltage waveform, the power on reset circuit should be designed with the same internal delay as the order of millisecond. Thus, the output signal of power-on reset circuit can set the firmware index to logic 0, as shown in Fig. 4.21(a). However, there are some mis-triggered conditions in power-on reset circuit. For example, fast power-up time (in the range of microsecond) may create difficult situations for the power-on reset circuit to work properly. Therefore a transient detection circuit is designed to sense fast electrical transients on power lines and combined with the power-on reset circuit in order to provide hardware/firmware co-design solution for system-level ESD issues.
Due to the difference in the rise times between the ESD voltage and the VDD power-on voltage, the on–chip transient detection circuit is designed to sense fast electrical transients and set the flag signal to logic 1, as shown in Fig. 4.21(b). Then, the firmware can execute the recover procedure to recover all the electrical functions to a stable state as soon as possible.
After the reset and recover procedures, the firmware index is reset to logic 0 again for detecting next electrical transient disturbance events.
By including the on-chip transient detection circuit and an additional firmware index into the chip, the firmware flowchart shown in Fig. 4.20 can be used to improve the system-level ESD and EFT robustness of microelectronic products. Such hardware/firmware co-design
method can provide an effective system solution to solve the system-level ESD and EFT issues in microelectronics system realized with CMOS ICs.
(a)
(b)
Fig. 4.21 Hardware/firmware operation during (a) power-on reset condition, and (b) system-level ESD stress.
4.6. Conclusion
A novel RC-based on-chip transient detection circuit I have been proposed and verified on silicon. The detection performance under different positive and negative electrical transients had been investigated by HSPICE. The experimental results have verified that the proposed on-chip transient detection circuit I can detect and memorize the occurrence of electrical transients due to system-level ESD and EFT zapping. In the system applications, the proposed on-chip transient detection circuit I can be further used as firmware recover index and combined with firmware design to provide an effective solution against the malfunction caused by system-level ESD or EFT zapping on microelectronic products.
Chapter 5
On-Chip Transient Detection Circuit Design for Electrical Transient Disturbance Protection (Scheme II)
A new on-chip transient detection circuit II is proposed to detect the electrical transient under the system-level ESD or EFT tests. It had been reported that the hardware/firmware co-design can effectively improve the transient disturbance susceptibility of CMOS ICs in microelectronic products. As the conceptual hardware/firmware co-design, when the electrical transient disturbance happens, the detection results from the on-chip transient detection circuit II can be stored as a firmware index to start the system recovery procedure after the disturbance. The circuit function to detect different positive or negative electrical transients has been investigated by HSPICE simulation and verified by silicon chip. The transient-induced latchup (TLU) measurement method, the system-level ESD gun, and the EFT generator are used to evaluate the detection function of the new proposed on-chip transient detection circuit. The experimental results in a 0.18-μm CMOS process have verified that the new proposed on-chip transient detection circuit II can successfully detect and memorize the occurrence of electrical transients during system-level ESD or EFT testing conditions.
5.1. Background
In order to protect microelectronic system against transient disturbance events, the traditional solution used in microelectronic products is to add some discrete noise-bypassing components or board-level noise filters into the printed circuit board (PCB) to decouple, bypass, or absorb the electrical transient energy under system-level electrical transient disturbance conditions. However, the additional discrete noise-bypassing components substantially increase the total cost of microelectronic products. Therefore, the chip-level solutions to meet high transient disturbance immunity specification for microelectronic products without additional discrete noise-decoupling components added on PCB are highly desired by IC industry.