Power-Rail ESD Clamp Circuits

To provide effective on-chip ESD protection, four different power-rail ESD clamp circuits had been reported [40]-[45], which are re-drawn in Figs. 2.2(a)-2.2(d) with the names of (1) power-rail ESD clamp circuit with typical RC-based detection, (2) power-rail ESD

clamp circuit with PMOS feedback, (3) power-rail ESD clamp circuit with NMOS+PMOS feedback, and (4) power-rail ESD clamp circuit with cascaded PMOS feedback, in this work.

Those power-rail ESD clamp circuits have been designed and fabricated in a 0.18-μm CMOS process to investigate their susceptibility to system-level ESD test.

(a)

(b)

(c)

(d)

Fig. 2.2 Four different power-rail ESD clamp circuits designed with (a) typical RC-based detection, (b) PMOS feedback, (c) NMOS+PMOS feedback, and (d) cascaded PMOS feedback.

2.2.1. Power-Rail ESD Clamp Circuit With Typical RC-Based Detection

The typical RC-based power-rail ESD clamp circuit is illustrated in Fig. 2.2(a) with a three-stage buffer between the RC circuit and the ESD-clamping NMOS [40]. The ESD-clamping NMOS is used to provide a low impedance path between VDD and VSS to

discharge ESD current. The ESD-transient detection circuit detects ESD pulses with the rise time of ~10ns and sends a control voltage to the gate of ESD-clamping NMOS. Under the ESD stress condition, the voltage level at the VFilter node is increased much slower than that on VDD power line, because the RC circuit has a time constant in the order of microsecond (μs). Due to the delay of the voltage increase at the VFilter node, the three-stage buffer is powered by the ESD energy and conduct a voltage to the VG node to turn on the ESD-clamping NMOS. The turned-on ESD-clamping NMOS, which provides a low-impedance path between VDD and VSS power lines, clamps the overstress ESD voltage to effectively protect the internal circuits against ESD damage.

The turn-on time of ESD-clamping NMOS during ESD transition can be adjusted by designing the RC time constant in the ESD transient detection circuit. The turn-on time is usually designed around ~100 ns to meet the half-energy discharging time of HBM ESD current. Under normal circuit operating conditions, the power-rail ESD clamp circuit must be kept off to avoid power loss from VDD to VSS. The rise time of VDD powered up is around

~1ms or even longer in the most of microelectronics systems. To meet such a timing requirement, the RC time constant in the RC-based ESD-transient detection circuit is typically designed with 0.1~1 μs to achieve the design constrains.

2.2.2. Power-Rail ESD Clamp Circuit With PMOS Feedback

Another design consideration for power-rail ESD clamp circuit is the circuit immunity to false triggering during power-up condition. The power-rail ESD clamp circuit should be turned on when the ESD voltage appears across VDD and VSS power lines, but kept off when the IC is under normal power-on condition. To meet these requirements, the RC time constant was usually designed with 0.1~1 μs to achieve the design constraints. However, the large RC time constant used in the power-rail ESD clamp circuit may cause false triggering during a fast power-up condition with a rise time of less than 10μs. The modified power-rail ESD clamp circuit incorporated with PMOS feedback, as shown in Fig. 2.2(b), was used to mitigate such a mis-trigger problem [41]. The transistor MPFB can help to keep the gate voltage of ESD-clamping NMOS below its threshold voltage and further reduce the current drawn during the power-up condition.

2.2.3. Power-Rail ESD Clamp Circuit With NMOS+PMOS Feedback

In the advanced CMOS technology with thinner gate oxide, the power-rail ESD clamp

circuit with a large MOS capacitance in the RC timer was reported to cause significant stand-by power consumption due to gate oxide leakage current [42]. Thus, the modified power-rail ESD clamp circuits with small MOS capacitance are desired to combat the gate leakage. It was reported that the power-rail ESD clamp circuit incorporated with a regenerative feedback network can be used to significantly reduce the RC time constant, as illustrated in Fig. 2.2(c) [43].

The transistors MPFB and MNFB provide a feedback loop, which can latch the ESD-clamping NMOS in the conductive state during ESD-stress condition. When a fast positive going ESD transient across the power rails, the MNFB can further pull the potential of INV2OUT node towards ground to latch the ESD-clamping NMOS in the conductive state until the voltage on VDD drops below the threshold voltage of ESD-clamping NMOS. With this feedback loop in the power-rail ESD clamp circuit, the dynamic currents of MP2, MN2, MPFB, and MNFB determine the critical voltage to trigger on the ESD-clamping NMOS.

After the timing out of the RC time constant in ESD transient detection circuit, the transistor MP2 begins to conduct and increase the potential of INVOUT2 node. The settling potential of INVOUT2 node is set by the current balance between MP2 and MNFB. Thus, the device ratios of MP2 and MNFB in the power-rail ESD clamp circuit with NMOS+PMOS feedback should be appropriately selected.

2.2.4. Power-Rail ESD Clamp Circuit With Cascaded PMOS Feedback

Another RC-based power-rail ESD clamp circuit with cascaded PMOS feedback has been proposed to reduce the RC time constant and to solve false trigger issue during fast power-up constrains, as shown in Fig. 2.2(d) [44]. The PMOS transistor MPFB is connected to form the cascaded feedback loop, which is a dynamic feedback design.

During the ESD-stress condition, the transistor MPFB was turned off and the voltage on the INV2OUT node can be remained in a low state. Thus, the turn-on time of the ESD-clamping NMOS can be longer than that of the typical RC-based power-rail ESD clamp circuit. If the ESD-clamping NMOS is mis-triggered during fast power-up condition or by an overvoltage under normal operating conditions, the voltage on the INV2OUT node can be charged up toward VDD by the subthreshold current of MPFB. Therefore, the ESD-clamping NMOS will not stay at latch-on state and turn itself off after the fast power-up condition.

Compared with the feedback designs with direct PMOS feedback in Fig. 2.2(b), the power-rail ESD clamp circuit with cascaded PMOS feedback has the advantage of

capacitance reduction.

2.2.5. Realization in Silicon Chip

For the four power-rail ESD clamp circuits in this work, the ESD-clamping NMOS is designed to turn on under the ESD-stress condition to efficiently discharge the ESD current between VDD and VSS power lines. The turn-on time of the ESD-clamping NMOS is designed to meet the half-energy discharging time of HBM ESD event. In the normal operating condition and VDD power-up condition, the ESD-clamping NMOS is designed to keep off to avoid power loss or false triggering. The four power-rail ESD clamp circuits in this work are designed with such design concepts to evaluate their susceptibility to system-level ESD tests.

To verify such a design, some simulations are provided in the following text. In Fig.

2.3(a), a VDD power-on voltage waveform with a rise time of 0.1ms and a voltage height of 1.8 V is applied to the VDD line of the power-rail ESD clamp circuits. During such a VDD

power-on condition, among the four different power-rail ESD clamp circuits, the voltage waveforms on the node VG are shown in Fig. 2.3(b), where the VG peak voltage during the power-on transition are all below the threshold voltage (~0.44 V) of the ESD-clamping NMOS. With a very small VG voltage in Fig. 2.3(b), the ESD-clamping NMOS in the four different power-rail ESD clamp circuits was expected to be always kept off when the IC is in normal operating conditions.

In Fig. 2.4(a), a fast ramp voltage with a rise time of 10ns is used to simulate the rising edge of HBM ESD pulse. The pulse height of the fast ramp voltage set as 5 V is used to monitor the voltage on the node VG before the drain breakdown of ESD-clamping NMOS. As shown in Fig. 2.4(b), among the four different power-rail ESD clamp circuits, the voltage waveforms on the node VG are simultaneously increased when the fast ramp voltage is applied to VDD, whereas the VSS is grounded. The four power-rail ESD clamp circuits are designed to provide a low impedance path between VDD and VSS power lines to efficiently discharge ESD current under ESD stress conditions. Combing with feedback circuit structure in the ESD-transient detection circuits, the turn-on time of the ESD-clamping NMOS can be increased by static or dynamic latches. For the power-rail ESD clamp circuits with NMOS+PMOS feedback and cascaded PMOS feedback, the turn-on time of the ESD-clamping NMOS can be longer than that of power-rail ESD clamp circuits with typical RC-based detection and PMOS feedback. The turn-on time of power-rail ESD clamp circuits with NMOS+PMOS feedback or cascaded PMOS feedback can be designed around 100ns, if

the RC time constant in the corresponding ESD-transient detection circuit is further reduced.

To simply the comparison for transient-induced latchup-like failure in this work, the RC values in the ESD-transient detection circuits among four power-rail ESD clamp circuits are set the same of R=50 kΩ and C=2 pF in silicon fabrication.

(a)

(b)

Fig. 2.3 HSPICE simulated voltage waveforms among the four different power-rail ESD clamp circuits under the VDD power-on condition. (a) A slow ramp voltage waveform with rise time of 0.1 ms is used to simulate the rising edge of the VDD power-on voltage. (b) The simulated voltage waveforms on the node VG when the power-on voltage is applied to VDD.

(a)

(b)

Fig. 2.4 HSPICE simulated voltage waveforms among the four different power-rail ESD clamp circuits under HBM ESD stress condition. (a) A fast ramp voltage waveform with rise time of 10 ns is used to simulate the rising edge of an HBM ESD pulse. (b) The simulated voltage waveforms on the node VG when the fast ramp voltage is applied to VDD.