System-Level ESD Tests

The proposed on-chip 4-bit transient-to-digital converter has been designed and fabricated in a 0.18-μm 1P5M CMOS process with 3.3-V devices. The fabricated chip in a package for system-level ESD test is shown in Fig. 6.11. The silicon area of proposed on-chip 4-bit transient-to-digital converter is 1030 μm x 188.5 μm.

Fig. 6.11 Die photo of the proposed on-chip 4-bit transient-to-digital converter.

The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under system-level ESD test with ESD voltage of +0.2 kV zapping on the HCP are shown in Fig. 6.12(a). During the fast transient of ESD stress, VOUT1, VOUT2, VOUT3, and VOUT4 are disturbed simultaneously during VDD and VSS disturbance.

Finally, VOUT1 will be changed from 0 V to 3.3 V with VOUT2, VOUT3, and VOUT4 are still kept at 0V. Therefore, under system-level ESD test with ESD voltage of +0.2 kV zapping, the output voltages of the proposed on-chip 4-bit transient-to-digital converter can be transferred into a thermometer digital code of “0001.”

The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under system-level ESD test with ESD voltage of +0.4 kV zapping on the HCP are shown in Fig. 6.12(b). During the fast transient of ESD stress, VOUT1, VOUT2, VOUT3, and VOUT4 are disturbed simultaneously during VDD and VSS disturbance.

Finally, VOUT1 and VOUT2 will be changed from 0 V to 3.3 V, with VOUT3 and VOUT4 are still kept at 0V. Therefore, under system-level ESD test with ESD voltage of +0.4 kV zapping, the output voltages of the proposed on-chip 4-bit transient-to-digital converter can be transferred into a thermometer digital code of “0011.”

The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under system-level ESD test with ESD voltage of +0.5 kV zapping on the HCP are shown in Fig. 6.12(c). During the fast transient of ESD stress, VOUT1, VOUT2, VOUT3, and VOUT4 are disturbed simultaneously during VDD and VSS disturbance.

Finally, VOUT1, VOUT2, and VOUT3 will be changed from 0 V to 3.3 V with VOUT4 is still kept at

0V. Therefore, under system-level ESD test with ESD voltage of +0.5 kV zapping, the output voltages of the proposed on-chip 4-bit transient-to-digital converter can be transferred into a thermometer digital code of “0111.”

The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under system-level ESD test with ESD voltage of +0.7 kV zapping are measured in Fig. 6.12(d). During the high-energy fast transient of ESD stress, all transient detection circuits can detect the occurrence of disturbance on VDD and VSS. Finally, when VDD finally returns to its normal stable voltage level, VOUT1, VOUT2, VOUT3, and VOUT4

have been changed from 0 V to 3.3 V. Therefore, under system-level ESD test with ESD voltage of +0.7 kV zapping, the output voltages of the proposed on-chip 4-bit transient-to-digital converter can be transferred into a thermometer digital code of “1111.”

(a) (b)

(c) (d)

Fig. 6.12 Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient voltage waveforms of the proposed on-chip 4-bit transient-to-digital converter under a system-level ESD test with an ESD voltage of (a) +0.2 kV, (b) +0.4 kV, (c) +0.5 kV, and (d) +0.7 kV, zapping on the HCP.

The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under system-level ESD test with ESD voltage of -0.2 kV zapping on the HCP are shown in Fig. 6.13(a). During the fast transient of ESD stress, VOUT1, VOUT2, VOUT3, and VOUT4 are disturbed simultaneously during VDD and VSS disturbance.

Finally, VOUT1 will be changed from 0 V to 3.3 V with VOUT2, VOUT3, and VOUT4 are still kept at 0V. Therefore, under system-level ESD test with ESD voltage of -0.2 kV zapping, the output voltages of the proposed on-chip 4-bit transient-to-digital converter can be transferred into a thermometer digital code of “0001.”

Similarly, Figs. 6.13(b), 6.13(c), and 6.13(d) show the measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under EFT tests with ESD voltages of -0.3 kV, -0.5 kV, and -1.4 kV zapping, and transferred into digital thermometer codes of “0011,” “0111,” and “1111,” respectively.

(a) (b)

(c) (d)

Fig. 6.13 Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient voltage waveforms of the proposed on-chip 4-bit transient-to-digital converter under a system-level ESD test with an ESD voltage of (a) -0.2 kV, (b) -0.3 kV, (c) -0.5 kV, and (d) -1.4 kV, zapping on the HCP.

Fig. 6.14 depicts the characteristic between ESD zapping voltages and the converted codes. With the proposed on-chip 4-bit transient-to-digital converter, different ESD voltages under system-level ESD tests can be detected and transferred into different thermometer digital codes. With larger ESD voltage level, the thermometer digital code goes higher, as listed in Table 6.1.

Fig. 6.14 The relationship between the ESD zapping voltage and the digital code in the proposed on-chip 4-bit transient-to-digital converter.

Table 6.1

ESD Voltage to Digital Code Characteristic of Proposed On-Chip 4-Bit transient-to-digital Converter

6.4.3. EFT Tests

The EFT generator combined with attenuation network shown in Fig. 4.16 is used to evaluate the detection function of the transient-to-digital converter under EFT tests.

The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under EFT test with an EFT voltage of +0.7 kV are shown in Fig. 6.15(a). During the EFT-induced fast transient, VOUT1, VOUT2, VOUT3, and VOUT4 are disturbed simultaneously during the VDD and VSS disturbance. Finally, VOUT1 will be changed from 0V to 3.3V while VOUT2, VOUT3, and VOUT4 remain 0V. Therefore, under EFT test with an EFT voltage of +700V zapping, the output voltages of the proposed on-chip 4-bit transient-to-digital converter can be transferred into a digital thermometer code of “0001.”

Similarly, Figs. 6.15(b), 6.15(c), and 6.15(d) show the measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under EFT tests with EFT voltages of +1.8 kV, +2.4 kV, and +3.4 kV, and transferred into digital thermometer codes of “0011,” “0111,” and “1111,” respectively.

(a) (b)

(c) (d)

Fig. 6.15. Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient voltage waveforms of the proposed on-chip 4-bit transient-to-digital converter under EFT test with EFT voltage of (a) +0.7 kV, (b) +1.8 kV, (c) +2.4 kV, and (d) +3.4 kV.

The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under EFT test with an EFT voltage of -0.6 kV are shown in Fig.

6.16(a). During the EFT-induced fast transient, VOUT1, VOUT2, VOUT3, and VOUT4 are disturbed simultaneously during the VDD and VSS disturbance. Finally, VOUT1 will be changed from 0 V to 3.3 V while VOUT2, VOUT3, and VOUT4 remain 0 V. Therefore, under EFT test with EFT voltage of -600 V zapping, the output voltages of the proposed on-chip 4-bit transient-to-digital converter can be transferred into a digital thermometer code of “0001.”

Similarly, Figs. 6.16(b), 6.16(c), and 6.16(d) show the measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of the proposed on-chip 4-bit transient-to-digital converter under EFT test with EFT voltages of -0.65 kV, -0.7 kV, and -0.8 kV, and transferred into digital thermometer codes of “0011,” “0111,” and “1111,” respectively.

(a) (b)

(c) (d)

Fig. 6.16. Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient voltage waveforms of the proposed on-chip 4-bit transient-to-digital converter under EFT test with EFT voltage of (a) -0.6 kV, (b) -0.65 kV, (c) -0.7 kV, and (d) -0.8 kV.

Fig. 6.17 depicts the relationship between the EFT zapping voltages and the converted codes. With the proposed on-chip 4-bit transient-to-digital converter, different EFT voltages under EFT tests can be detected and transferred into different digital thermometer codes.

With a larger EFT voltage level, the digital thermometer code goes higher, as listed in Table 6.2.

Fig. 6.17. The relationship between the EFT voltage level and the digital code in the proposed on-chip 4-bit transient-to-digital converter.

Table 6.2

EFT Voltage to Digital Code Characteristic of Proposed On-Chip 4-Bit transient-to-digital Converter