Transient-Induced Latchup in CMOS Integrated Circuits under EFT Tests
3.3. Experimental Measurements
(b)
Fig. 3.4 (a) Equivalent circuit schematic of SCR device. (b) I-V characteristics of SCR device under positive and negative biases.
3.3. Experimental Measurements
The TLU measurement setup under EFT tests is sketched in Fig. 3.5. The EFT generator can generate the positive and negative transient EFT pulses on power pins of the device under
test (DUT). The SCR device shown in Figs. 3.3(a) and 3.3(b) is used as the DUT where the anode (cathode) of SCR is connected to VDD (ground). IDD is the total current flowing into the anode of SCR. The IDD current waveform is monitored by a separated current probe. The current-limiting resistance (5 Ω) is used to protect the DUT from electrical-over-stress (EOS) damage during a high-current (low-impedance) latchup state. With both positive and negative EFT voltages, the measured VDD (IDD) transient response is recorded through the voltage (current) probe on the oscilloscope. This clearly indicates whether TLU occurs (IDD
significantly increases) during the TLU tests with EFT pulses.
Fig. 3.5 Measurement setup for TLU under EFT tests.
3.3.1. TLU Tests with EFT Generator
With a negative EFT voltage of -200 V, the measured VDD and IDD transient responses on the SCR structure are shown in Fig. 3.6(a). In the beginning with normal power supply (VDD=3.3 V, VSS=0 V), the SCR operates in the off state and VDD is kept at the normal operating voltage (+3.3 V). Within this duration before EFT pulse applied, the N-well/P-well junction is in a normal reverse-biased state, and IDD only comes from the negligible leakage current in the reverse junction. When the EFT pulse is applied with a negative EFT voltage, VDD begins to decrease rapidly from +3.3 V and will eventually reach the negative peak voltage. Within this duration, the N-well/P-well junction becomes forward biased when VDD
drops below 0V. Thus, the forward-biased N-well/P-well junction can generate the forward current. When VDD increases from the negative peak voltage back to its normal operating voltage (+3.3 V), the N-well/P-well junction will rapidly change from the forward-biased state to the reverse-biased state. Meanwhile, inside the N-well (P-well) region, a large number of stored minority holes (electrons) offered by the forward peak current will be instantaneously “swept-back” to the P-well (N-well) region where they originally come from.
Therefore, such “sweep-back” current, ISb, will produce a localized voltage drop and flow through the parasitic P-well or N-well resistance. Once this localized voltage drop approaches the cut-in voltage of the PN junction, the emitter-base junction of either the vertical PNP or the lateral NPN BJT in the SCR structure will be forward biased to further trigger on latchup.
Afterwards, IDD will greatly increase while VDD returns to above 0V, which indicates the occurrence of latchup. After EFT tests, VDD will eventually be pulled down to the latchup holding voltage (+1.5 V), as shown in Fig. 3.6(a). Finally, the VDD (IDD) waveform is locked at a low voltage (high current) latchup state after this transition induced by the EFT pulse.
From the measured results in Fig. 3.6(a), the occurrence TLU in SCR under EFT test had been observed because the huge IDD of ~160 mA can be found and VDD finally pulls down to the holding voltage (+1.5 V). TLU will be triggered on due to large enough ISb while VDD
returns from negative peak voltage to the positive voltage.
With a positive EFT voltage of +200 V, the measured VDD and IDD transient responses on the SCR structure are shown in Fig. 3.6(b). Unlike the VDD waveform with a negative EFT voltage shown in Fig. 3.6(a), where VDD begins decreasing rapidly, VDD starts to increase and reaches a positive peak voltage. Within this duration, the N-well/P-well junction is always reverse biased within the SCR. Afterwards, VDD decreases from the positive peak voltage to the negative peak voltage. Within this duration, the N-well/P-well junction gradually changes from the reverse-biased state to the forward-biased state, while more minority electrons (holes) are injected into the P-well (N-well) region. When VDD returns from the negative peak voltage to the positive voltage, these minority electrons (holes) are subsequently swept back to the N-well (P-well) regions where they originally come from and finally TLU is triggered on. As a result, IDD will considerably increase when VDD returns from the negative peak voltage to the positive voltage. After the EFT test, TLU occurs because the huge IDD of ~160 mA can be found and VDD eventually pulls down to its latchup holding voltage of +1.5 V, as shown in Fig. 3.6(b).
The SCR structure in bulk CMOS processes is very susceptible to TLU under an EFT pulse as low as ±200 V. Due to such weak immunity against TLU under EFT tests, some
latchup prevention methods should be provided to improve TLU immunity of CMOS ICs.
(a)
(b)
Fig. 3.6 Measured VDD and IDD transient waveforms on SCR test structure under EFT tests with EFT voltage of (a) -200 V, and (b) +200 V.
3.3.2. Physical Mechanism
Under the EFT test with the negative voltage pulse, it has been proved that the swept-back current, ISb, caused by the minority carrier stored within the parasitic PNPN structure of CMOS ICs is the major cause of the TLU. For the sake of simplicity, two reasonable assumptions are made. First, the N-well/P-well junction is treated as an ideal 1-D diode with step junction profile, as in the inset figure shown in Fig. 3.7. Second, the storage time of minority carriers is assumed to be negligible because IDD can rapidly follow the polarity variation of VDD. Therefore, from the assumptions, the stored minority holes (QStored) inside the N-well region can be expressed as
'⎡ ( , ) = ( , ) = ⎤
=
∫
Xnn ⎣ B − A⎦Stored X n t t n t t
Q P x t P x t dx , (1)
where Pn(x,t) is the hole concentration in the N-well region and tA (tB) is the initial (final) timing point of a specific duration when ISb exists. QStored represents the total stored minority carriers (holes) causing ISb (tA≤t≤tB) inside the N-well region. Compared with the quasi-static latchup test, the specific duration (tA≤t≤tB) in the EFT test is much shorter than that in the quasi-static latchup test because the EFT pulse duration is only several tens of nanoseconds [19]. The rise time (fall) time for the quasi-static latchup test is much longer (~μs) than that for the EFT test. Thus, once these QStored are swept back to the regions where they come from, the averaged ISb can be expressed as
In both TLU and quasi-static latchup conditions, if the initial (t=tA) and the final (t=tB) voltages during tA≤t≤tB are equal (i.e., with the same amount QStored), the averaged ISb in the TLU case will be about 103~106 times larger than that in the quasi-static latchup case. The averaged ISb is rather small and hard to trigger on latchup in the quasi-static latchup test.
Therefore, the averaged ISb is large enough to easily trigger on latchup in the SCR structure under the EFT test.
The physical mechanism of TLU under the EFT tests can be well proved by comparing the experimental results. As shown in Figs. 3.6(a) and 3.6(b), large enough ISb caused by the instantaneously forward-biased N-well/P-substrate junction can easily trigger on TLU under EFT tests with positive and negative EFT voltages.
Fig. 3.7 The total stored minority carriers, QStored, causing ISb (tA≤t≤tB) inside the N-well region. The inset figure is an ideal 1-D diode used for deriving the 1-D analytical model of the averaged ISb (≡IAve).