System-Level ESD Zapping Conditions

Figs. 4.3(a) and 4.3(b) show the measured transient voltage waveform on the power line of CMOS ICs inside the EUT with ESD voltages of +1 kV and -1 kV, respectively. The power lines (pins) of the CMOS ICs no longer maintain their normal voltage levels, but acts as an underdamped sinusoidal voltage instead.

From the measured electrical transient waveform shown in Figs. 4.3(a) and 4.3(b), the underdamped sinusoidal voltage waveform on power line of CMOS IC during the system-level ESD stress has been observed. There, a sinusoidal time-dependent voltage source with damping factor parameter is given by

( )= 0+ _a⋅sin(2 ( − _d)) exp( (⋅ − − _d) _a).

V t V V πf t t t t D (1)

It is used to simulate an underdamped sinusoidal voltage on the VDD and VSS lines of the proposed on-chip transient detection circuit I, as shown in Fig. 4.4. With the proper parameters such as the applied voltage amplitude Va, initial dc voltage V0, damping factor Da, damping frequency f (=DFreq), and time delay td, the underdamped sinusoidal voltage can be

used to simulate the electrical transient waveforms under system-level ESD tests. In the HSPICE simulation with positive-going or negative-going underdamped sinusoidal waveforms, the same parameters of Da= 2x10⁷ s^-1, f= 50 MHz, and td= 500 ns are used (which is corresponding to the measured transient waveform in Figs. 4.3(a) and 4.3(b)). For the positive-going underdamped sinusoidal waveform, the polarity of Va parameter is positive.

For the negative-going underdamped sinusoidal waveform, the polarity of Va parameter is negative. In addition, V0 is 3.3 V (0 V) as the initial dc voltage on the VDD (VSS) line of the proposed on-chip transient detection circuit I.

(a)

(b)

Fig. 4.3 Measured voltage waveforms with ESD voltage of (a) +1 kV, and (b) -1 kV

Fig. 4.4 The specific time-dependent underdamped sinusoidal waveforms applied on the power and ground lines to simulate the transient disturbance under system-level ESD zapping.

The simulated VDD, VSS, and VOUT waveforms of the proposed on-chip transient detection circuit I with a positive-going underdamped sinusoidal voltage on both VDD and VSS are shown in Fig. 4.5(a). The positive-going underdamped sinusoidal voltage with Va of +8 V on VDD and with Va of +4 V on VSS are used to simulate the larger overshooting voltage coupled on VDD

under the system-level ESD test, as shown in Fig. 4.5(a). Under ESD stress, VDD (VSS) begins to increase rapidly from 3.3 V (0 V) to 11 V (4 V). VOUT is disturbed simultaneously during the VDD and VSS disturbance. During this period, the proposed on-chip RC-based transient detection circuit I can detect the occurrence of disturbances on VDD and VSS. As a result, after VDD finally returns to its normal voltage level of 3.3 V, VOUT will be changed from 0 V to 3.3 V, as shown in Fig. 4.5(a).

The simulated VDD, VSS, and VOUT waveforms of the proposed on-chip transient detection circuit I with a positive-going underdamped sinusoidal voltage on both VDD and VSS are shown in Fig. 4.5(b). The positive-going underdamped sinusoidal voltage with Va of +4 V on VDD and with Va of +8 V on VSS are used to simulate the larger overshooting voltage coupled on VSS

under the system-level ESD test, as shown in Fig. 4.5(b). The VOUT is influenced by the VDD and VSS disturbance through the coupling paths. Finally, the output (VOUT) of the proposed on-chip transient detection circuit is changed from 0 V to 3.3 V.

(a)

(b)

Fig. 4.5 Simulated VDD, VSS, and VOUT waveforms of the proposed transient detection circuit I under system-level ESD test with larger overshooting voltage coupled on (a) VDD, and (b) VSS.

Under the negative system-level ESD zapping condition, the simulated VDD, VSS, VOUT1, and VOUT2 waveforms of the proposed transient detection circuit with a negative-going underdamped sinusoidal voltage on VDD and VSS are shown in Figs. 4.6(a) and 4.6(b). The negative-going underdamped sinusoidal voltages with Va of -8 V on VDD and with Va of -4 V on VSS are used to simulate the larger undershooting voltage coupled on VDD under the system-level

ESD test, as shown in Fig. 4.6(a). The negative-going underdamped sinusoidal voltages with Va

of -4 V on VDD and with Va of -8 V on VSS are used to simulate the larger undershooting voltage coupled on VSS under the system-level ESD test, as shown in Fig. 4.6(b). In Figs. 4.6(a) and 4.6(b), the output voltage of the transient detection circuit I begins to decrease rapidly. The VOUT1 and VOUT2 are influenced by the VDD/VSS disturbance. Finally, the output voltages (VOUT1

and VOUT2) of the transient detection circuit I are changed from 0V to 3.3 V, as shown in Figs.

4.6(a) and 4.6(b).

(a)

(b)

Fig. 4.6 Simulated VDD, VSS, and VOUT waveforms of the proposed transient detection circuit I under system-level ESD test with larger undershooting voltage coupled on (a) VDD, and (b) VSS.

On the PCB design with CMOS IC products, the trace routing placements may be different for power (VDD) lines and ground (VSS) lines. This will cause different signal paths from ESD source to VDD and VSS pins of the chip, as shown in Fig. 4.7(a). The different signal paths may result in different signal delays between VDD and VSS waveforms. As shown in Fig. 4.7(b), 5-ns signal delay has been observed between VDD and VSS pins of the chip.

Therefore, the different signal delays in the transient waveforms between VDD and VSS should be taken into consideration in the design of the proposed on-chip transient detection circuit

(a) (b)

Fig. 4.7 (a) Different signal coupling path from the ESD zapping source to VDD and VSS pins of CMOS IC on the PCB. (b) Time delay between the measured VDD and VSS waveforms is due to the different coupling path.

The simulated VDD, VSS, and VOUT waveforms of the proposed transient detection circuit I with signal delay between VDD and VSS waveforms are shown in Figs. 4.8(a) and 4.8(b). In order to simulate the signal delay condition that VDD signal leads the VSS signal, different td

parameters are used on VDD (td =500 ns) and VSS (td =505 ns) voltage sources. The positive Va

on VDD and VSS waveforms is used in this simulation for signal delay condition, as shown in Fig. 4.8(a). The negative Va on VDD and VSS waveforms is used in this simulation for another signal delay condition, as shown in Fig. 4.8(b). During the period with electrical transient disturbance, VOUT is influenced with the VDD/VSS waveforms and acts as underdamped sinusoidal voltage waveform. After the simulated electrical transient disturbance, VOUT is pulled up to the voltage level of 3.3 V. With a signal delay between VDD and VSS, the

proposed on-chip transient detection circuit I can still memorize the occurrence of electrical transients on VDD and VSS lines.

(a)

(b)

Fig. 4.8 Simulated VDD, VSS, and VOUT waveforms of the proposed transient detection circuit I under (a) positive, and (b) negative underdamped sinusoidal voltage on VDD/VSS power lines with signal delay condition.