System-level ESD Tests

In the IEC 61000-4-2 standard, two test modes have been specified, which are the air-discharge test mode and the contact-discharge test mode. Contact discharge is further divided into direct discharge to the system under test, and indirect discharge to horizontal or vertical coupling planes. Fig. 4.14 shows the standard measurement setup of the system-level ESD test in the indirect contact-discharge test mode. The measurement setup for system-level

ESD test consists of a wooden table on the grounded reference plane (GRP). In addition, an insulation plane is used to separate the EUT from the horizontal coupling plane (HCP). The HCP are connected to the GRP with two 470 kΩ resistors in series. When the ESD gun zaps the HCP, the EMI coming from ESD will be coupled into all CMOS ICs inside EUT. The power lines of CMOS ICs inside EUT will be disturbed by the ESD-coupled energy.

Fig. 4.14 Measurement setup of system-level ESD test with indirect contact discharge mode.

With such a standard measurement setup, the circuit performance of the proposed on-chip RC-based transient detection circuit I under system-level ESD tests can be evaluated.

By using the digital oscilloscope, the transient responses on power lines of CMOS IC products can be recorded and analyzed. Before each system-level ESD zapping, the initial output voltage (VOUT) of the proposed on-chip RC-based transient detection circuit I is reset to 0 V. After each system-level ESD zapping, the output voltage (VOUT) level is measured to check the final voltage level and to verify the detection function. Thus, the circuit performance of the proposed on-chip RC-based transient detection circuit I can be directly evaluated with this measurement setup.

The measured VDD and VOUT waveforms of the proposed on-chip RC-based transient detection circuit I under a system-level ESD test with the ESD voltage of +0.2 kV zapping on the HCP is shown in Fig. 4.15(a). VDD begins to increase rapidly from the normal voltage (+3.3 V). Meanwhile, VOUT begins to change under such a high-energy ESD stress. During the fast transient disturbance, VDD and VOUT are influenced simultaneously. Finally, the output voltage of

the proposed on-chip RC-based transient detection circuit I has been changed from 0 V to 3.3 V.

The measured VDD and VOUT transient waveforms of the proposed on-chip RC-based transient detection circuit with an ESD voltage of -0.2 kV zapping on the HCP under system-level ESD test are shown in Fig. 4.15(b). During the VDD disturbance, VOUT is disturbed simultaneously. VOUT is finally pulled up to 3.3 V after the system-level ESD test. Therefore, the proposed on-chip RC-based transient detection circuit I can sense the fast electrical transient on the power lines and memorize the occurrence of system-level ESD events.

(a)

(b)

Fig. 4.15 Measured VDD and VOUT transient responses of the proposed transient detection circuit I under system-level ESD test with ESD voltage of (a) +0.2 kV, and (b) -0.2 kV zapping on the HCP.

4.4.3. EFT Tests

4.4.3.1. With Attenuation Network

In order to simulate the EFT-induced transient disturbance on CMOS ICs inside the microelectronic products, the attenuation network with 200 dB degradation is used in this work. The amplitude of EFT-induced transients can be adjusted through the attenuation network.

The measurement setup for EFT test combined with attenuation network is shown in Fig.

4. 16. A supply voltage of 3.3 V is used as VDD and EFT generator is connected to the DUT through the attenuation network. The VDD and VOUT transient responses of the novel proposed on-chip transient detection circuit I are monitored by the digital oscilloscope. With such a measurement setup, the circuit function of the novel proposed on-chip transient detection circuit I after EFT tests can be evaluated. Before each EFT testing, the initial output voltage (VOUT) of the novel proposed on-chip transient detection circuit I is reset to 0 V. After each EFT testing, the output voltage (VOUT) level is measured to check the final voltage level and to verify the detection function. Thus, the detection function of the novel proposed on-chip transient detection circuit I can be directly evaluated with the measurement setup of EFT tests combined with attenuation network.

Fig. 4.16 Measurement setup for EFT test combined with attenuation network.

As shown in Fig. 4.17(a), under the EFT test with input EFT voltage of +500 V, VDD

begins to increase rapidly from 3.3 V and acts like positive exponential voltage pulse. During the EFT test, VOUT is influenced simultaneously with positive exponential voltage pulse

coupled to VDD power line. After the EFT test with the input EFT voltage of +500 V, the output voltage (VOUT) of the novel proposed on-chip transient detection circuit I transits from 0 V to 3.3 V. As shown in Fig. 4.17(b), under the EFT test with input EFT voltage of -500 V, VDD begins to decrease rapidly from 3.3 V and acts like negative exponential voltage pulse.

During the EFT test, VOUT is influenced simultaneously with negative exponential voltage pulse coupled to VDD power line. After the EFT test with the input EFT voltage of -500 V, the output voltage (VOUT) of the novel proposed on-chip transient detection circuit I transits from 0 V to 3.3 V.

(a)

(b)

Fig. 4.17 Measured VDD and VOUT waveforms on the proposed on-chip transient detection circuit I under EFT tests with (a) positive, and (b) negative EFT voltages.

4.4.3.2. With Capacitance Coupling Clamp

In standard of IEC 61000-4-4, the capacitive coupling clamp has been recommended as another measurement setup to couple the EFT testing voltages into the EUT.

The capacitive coupling clamp provides the ability of coupling the fast transients and bursts to the circuit under test without any galvanic connection to the terminals of the EUT, shielding of the cables or any other part of the EUT. The coupling capacitance of the clamp depends on the diameter, material of the cables, and shielding. The typical coupling capacitance between the cable and clamp ranges from 50 pF to 200 pF. The capacitive coupling clamp is composed of a clamp unit (made of galvanizes steel, brass, copper, or aluminium) for housing the cables (flat or round) connected to the circuit under test and should be placed on the ground plane with minimum area of 1 m². The line should be provided at both ends with a high-voltage coaxial connector for the connection of EFT generator at either end. EFT generator is connected to the end of the clamp which is nearest to the EUT. The capacitive coupling clamp itself should be closed as much as possible to provide maximum coupling capacitance between the cable and the clamp.

The measurement setup for EFT test combined with capacitive coupling clamp is shown in Fig. 4.18. A supply voltage of 3.3 V is used as VDD and the capacitive coupling clamp is connected with EFT generator to directly couple the EFT testing voltages into the VDD cable line. The VDD and VOUT voltage waveforms of the novel proposed on-chip transient detection circuit I are monitored by the digital oscilloscope during the EFT tests. With such a measurement setup, the circuit function of the novel proposed on-chip transient detection circuit I under EFT tests combined with capacitive coupling clamp can be evaluated.

Fig. 4.18 Measurement setup for EFT test combined with capacitive coupling clamp.

Figs. 4.19(a) and 4.19(b) show the measured VDD and VOUT transient responses of the novel proposed on-chip transient detection circuit I under the EFT test with input EFT voltages of +200 V and -200 V, respectively.

(a)

(b)

Fig. 4.19 Measured VDD and VOUT transient voltage waveforms of the proposed on-chip transient detection circuit I under EFT tests with EFT voltage of (a) +200 V, and (b) -200 V by combining with capacitive coupling clamp.

As shown in Fig. 4.19(a), under the EFT tests with input EFT voltage of +200 V, VDD

begins to increase rapidly from 3.3 V and acts like positive-going underdamped sinusoidal voltage waveform. During the EFT test, VOUT is influenced simultaneously with

positive-going underdamped sinusoidal voltage coupled to VDD power line. After the EFT test with the input EFT voltage of +200 V, the output voltage (VOUT) of the novel proposed on-chip transient detection circuit I transits from 0 V to 3.3 V.

As shown in Fig. 4.19(b), under the EFT test with EFT voltage of -200 V, VDD begins to decrease rapidly from 3.3 V and acts like negative-going underdamped sinusoidal voltage waveform. During the EFT test, VOUT is influenced simultaneously with negative-going underdamped sinusoidal voltage coupled to VDD power line. After the EFT test with the input EFT voltage of -200 V, the output voltage (VOUT) of the novel proposed on-chip transient detection circuit I transits from 0 V to 3.3 V.

From the EFT test results shown in Fig. 4.19(a) and 4.19(b), with positive-going or negative-going underdamped sinusoidal voltage waveforms coupled to VDD power line, the output voltages (VOUT) of the novel proposed on-chip transient detection circuit I can be changed from 0V to the voltage level of 3.3 V. Therefore, the novel proposed on-chip transient detection circuit I can successfully memorize the occurrence of positive-going or negative-going EFT-induced underdamped sinusoidal transient disturbance.