Electrical Fast Transient (EFT) Test

The measurement setup for EFT test is shown in Fig. 2.14. The supply voltage of 1.8 V is used as VDD and the EFT generator is connected directly to the device under test (DUT) through the cable in this work. The voltage and current waveforms on the DUT (at VDD node) after EFT test are monitored by the digital oscilloscope. With such a standard measurement setup, the susceptibility of different power-rail ESD clamp circuits against the EFT tests can be evaluated. The stand alone power-rail ESD clamp circuit in IC package is powered up with power supply of 1.8 V. Before any EFT zapping, the initial VDD voltage level on the IC is measured to make sure the correct bias of 1.8 V. After every EFT voltage zapping, the voltage level on VDD node of IC is measured again to watch whether latchup-like failure occurs after the EFT test, or not. If the latchup-like failure occurs, the potential on VDD node will be pulled down to a much lower level due to the latch-on state of ESD-clamping NMOS in the power-rail ESD clamp circuits, and IDD will be significantly increased.

Fig. 2.14 Measurement setup for EFT test with IC power supply of 1.8 V.

With the EFT measurement setup shown in Fig. 2.14, the VDD and IDD transient responses can be recorded by the oscilloscope, which can clearly indicate whether the latchup-like failure occurs or not. Figs. 2.15(a) and 2.15(b) show the measured VDD and IDD transient responses on the power-rail ESD clamp circuit with typical RC-based detection when EFT generator with EFT voltage of -800 V and +800 V zapping, respectively. After the EFT test with an EFT voltage of -800 V, latchup-like failure is not initiated in this power-rail ESD clamp circuit, because IDD is still kept at zero, as shown in Fig. 2.15(a). After the EFT test

with an EFT voltage of +800 V, latchup-like failure is not observed in Fig. 2.15(b).

(a)

(b)

Fig. 2.15 Measured VDD and IDD waveforms on the power-rail ESD clamp circuit with typical RC-based detection under EFT test with EFT voltage of (a) -800 V, and (b) +800 V.

Under EFT test with EFT voltage of -800 V and +800 V, the measured VDD and IDD

transient waveforms on the power-rail ESD clamp circuit with PMOS feedback are shown in Figs. 2.16(a) and 2.16(b), respectively. Under EFT test with an EFT voltage of -800 V (+800

V), VDD acts with the EFT-induced trigger. Meanwhile, latchup-like failure does not occur because IDD is not increased, as shown in Fig. 2.16(a) (Fig. 2.16(b)). For the power-rail ESD clamp circuits with typical RC-based detection or PMOS feedback, latchup-like failure does not occur even though the EFT voltage is as high as -800 V or +800 V in the EFT test.

(a)

(b)

Fig. 2.16 Measured VDD and IDD waveforms on the power-rail ESD clamp circuit with PMOS feedback under EFT test with EFT voltage of (a) -800 V, and (b) +800 V.

Figs. 2.17(a) and 2.17(b) show the measured VDD and IDD transient responses on the power-rail ESD clamp circuit with NMOS+PMOS feedback under the EFT test with EFT voltages of -200 V and +200 V, respectively. After the EFT test with an EFT voltage of -200 V, latchup-like failure can be initiated in this power-rail ESD clamp circuit, because IDD is significantly increased and VDD is pulled down as shown in Fig. 2.17(a). After the EFT test with an EFT voltage of +200 V, the latchup-like failure can be also found in Fig. 2.17(b).

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(b)

Fig. 2.17 Measured VDD and IDD waveforms on the power-rail ESD clamp circuit with NMOS+PMOS feedback under EFT test with EFT voltage of (a) -200 V, and (b) +200 V.

All the PMOS and NMOS devices in the ESD-transient detection circuits are surrounded with double guard rings to guarantee no latchup issue in this part. This implies that the feedback loop in the ESD-transient detection circuit is locked after EFT test and continually keeps the ESD-clamping NMOS in the latch-on state. From the observed voltage and current waveforms, large IDD current is caused by the latch-on state of ESD-clamping NMOS after EFT tests.

For the power-rail ESD clamp circuit with cascaded PMOS feedback, the measured VDD

and IDD transient responses are shown in Figs. 2.18(a) and 2.18(b) under the EFT test with EFT voltages of -200 V and +500 V, respectively. The similar latchup-like failure also occurs in this power-rail ESD clamp circuit due to the latch-on state of ESD-clamping NMOS under the EFT test with an EFT voltage of -200 V, as shown in Fig. 2.18(a).

The susceptibility among the aforementioned four different power-rail ESD clamp circuits against EFT tests are listed in Table 2.3. The power-rail ESD clamp circuits with NMOS+PMOS feedback or with cascaded PMOS feedback have lower EFT voltages to cause latchup-like failure after EFT test. From the experimental results, the power-rail ESD clamp circuit designed with NMOS+PMOS feedback is highly sensitive to transient-induced latchup-like failure. The typical power-rail ESD clamp circuits with RC-based detection and with PMOS feedback are free to such a latchup-like failure.

Table 2.3

Comparison on Susceptibility among Four Different Power-Rail ESD Clamp Circuits Against EFT Tests

(a)

(b)

Fig. 2.18 Measured VDD and IDD waveforms on the power-rail ESD clamp circuit with cascaded PMOS feedback under EFT test with EFT voltage of (a) -200 V, and (b) +500 V.

Latchup-like failure in this EFT test.

The failure location after EFT test has been inspected, as shown in Fig. 2.19. The failure location is located at the VDD metal line from the VDD pad to the power-rail ESD clamp circuit, which was drawn with a metal width of 30 μm in the test chip.

Fig. 2.19 Failure location of power-rail ESD clamp circuit after EFT tests.