Conclusions and Future Works
7.2. Future Works
In addition to using the on-chip transient detection circuits and transient-to-digital converters proposed in this dissertation, some other techniques could be the useful candidates to further improve the susceptibility of the CMOS ICs against the system-level ESD or EFT tests. These future works are listed below.
(1) Linear Relationship between the ESD/EFT Zapping Voltages and Digital Codes (2) Hardware and Firmware Co-Design with System-Auto-Reset Function
(3) Latchup Auto-Detection, Self-Stop, and Auto-Reset Circuit (4) Layout Optimization
(5) Other Specific Advanced Process Technologies
With the developments of future system-level ESD and EFT prevention techniques, it is anticipated that electrical transient disturbance events can be efficiently suppressed in the continual-scaling CMOS technologies.
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VITA
姓 名：顏承正 (Cheng-Cheng Yen)
性 別：男
出生日期：民國65 年 5 月 13 日 出 生 地：新竹市
住 址：新竹市光復路 2 段 10 巷 15 號
學 歷：國立交通大學電機與控制工程系畢業 (83 年 9 月 - 87 年 6 月)
國立交通大學電子研究所碩士班 (87 年 9 月 - 89 年 6 月)
國立交通大學電子研究所博士班 (89 年 9 月入學)
論文名稱：互補式金氧半積體電路之系統層級靜電放電防護設計
System-Level ESD Protection Design in CMOS ICs with Transient Detection Circuits