高速除頻電路與正交相位振盪器之設計

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(1)! !!!!୯!ҥ!Ҭ!೯!ε!Ꮲ!. ! ႝߞπำᏢ‫!س‬ ! ᅺ!γ!ፕ!Ў! ! !. ଯೲନᓎႝၡᆶ҅Ҭ࣬ՏਁᕏᏔ ϐ೛ी ! Design and Implementation of High Speed Frequency Dividers and Quadrature VCOs ! ! ! ࣴ‫ز‬ғǺ஭ӹЎ! ! ࡰᏤ௲௤Ǻ‫ۏ‬ቼ‫ے‬௲௤! ! ! ύ! ๮! ҇! ୯! !ΐΜѤ!! ԃ! !Ύ! !Д!.

(2) ଯೲନᓎႝၡᆶ҅Ҭ࣬ՏਁᕏᏔϐ೛ी Design and Implementation of High Speed Frequency Dividers and Quadrature VCOs ࣴ‫ز‬ғǺ஭ӹЎ. Student: Yu-Wen Chang. ࡰᏤ௲௤Ǻ‫ۏ‬ቼ‫ ے‬റγ Advisor: Dr. Chin Chun Meng ୯ ҥ Ҭ ೯ ε Ꮲ ႝߞπำ‫س‬ᅺγ੤ ᅺγፕЎ A Thesis Submitted to Institute of Communication Engineering College of Electric Engineering and Computer Science National Chiao Tung University In Partial Fulfillment of the Requirements For the Degree of Master of Science In Communication Engineering. June 2005 Hsinchu, Taiwan, Republic of China ύ๮҇୯ΐΜѤԃΎД.

(3) ! ! ύЎᄔा! ! ҁፕЎჴբ೽ϩх֖ଯೲନᓎႝၡᆶ҅Ҭ࣬ՏਁᕏᏔ‫ޑ‬೛ीǶ ճҔ GCT 2.0 um InGap/GaAs HBT Ϸ TSMC 0.35µm SiGe BiCMOS ϐᇙำǴӧନᓎႝၡБय़ჴ౜ΑǺ(1)ёᏹբӧ2~7.4GHz ‫ޑ‬ᓉᄊନᓎ ႝၡǹ(2)ёᏹբӧ2~11GHz ‫୏ޑ‬ᄊନᓎႝၡǹ(3)ёᏹբӧ6~9.7GHz ‫ޑ‬ຬ୏ᄊନᓎႝၡǹ(4)ёᏹբӧ9.636~10.246GHz ‫ࠠᙹݙޑ‬ନᓎႝ ၡǹ(5)ёᏹբӧ7~27GHz ‫ޑ‬ӣൺࠠନᓎႝၡǹ(6)ёᏹբ0.25~3.8GHz ‫ޑ‬ø4/5ႝၡǹа΢ႝၡନΑᓎ౗όӕѦᗋԖঁձ‫ޑ‬ᓬલᗺǴё٩‫س‬಍ ‫ޑ‬ሡ‫؃‬ᒧ᏷٬ҔǴ၁ಒ‫ޑ‬ᇥܴஒӧҁЎύుΕ௖૸Ƕӧ҅Ҭ࣬Տਁ ᕏᏔБय़Ǵჴ౜Α᠄ௗጠӝԄ‫ک‬Β໘ᒋ‫ݢ‬ጠӝ‫ࢎޑ‬ᄬǴ‫ࢎٿ‬ᄬ‫࣬ޑ‬ Տᚇૻ‫࣬ک‬ՏᇤৡϕԖᓬӍǴё٩ԏวᐒ‫ޑ‬ೕ਱ा‫؃‬᏷ᓬ٬ҔǶԜ ѦӧਁᕏᏔ‫ޑ‬೛ी΢ΨගрΑཥ‫ࢎޑ‬ᄬǴႣය཮Ԗόᒱ‫ޑ‬ႝၡ੝‫܄‬ ߄౜Ƕ. i.

(4) ! ! Abstract. ! This thesis presents the design of high speed frequency dividers and quadrature voltage controlled oscillators. First, we use GCT 2.0 um InGap/GaAs HBT and TSMC 0.35µm SiGe BiCMOS processes to implement the two kinds of circuits. In frequency divider circuits, have implemented several structures as followerǺ(1)Static frequency divider can operate from 2 to 7.4GHz. (2)Dynamic frequency divider can operate from 2 to 11GHz. (3)Superdynamic frequency divider can operate from 6 to 9.7GHz. (4)Injection locked frequency divider can operate from 9.636 to 10.246GHz. (5)Regenerative frequency divider can operate from 7 to 27GHz, and (6)Dual modulus frequency divider(ø4/5) can operate from 0.25 to 3.8GHz. Those circuits have particular characteristics and can be chosen to fit the specs of the system. The detail expansions will be discussed in the following chapters. Also, the realization of top-series and superharmonic coupling quadrature VCOs are shown in this thesis. One has a better phase noise than the other, but a worse phase error than. ii.

(5) the other. Each topology can be used in a transceiver that has different requirements of phase noise and phase error. Finally, a new structure of VCO is presented. Depending on the theories and simulations, the performance of the circuit might be better than the others.. iii.

(6) ᇞᖴ ೭ࢂӧբფ༏ǻ‫ך‬ഖฅவფ൦а‫ޑ؃‬Ҭ೯εᏢႝߞ‫܌‬౥཰ΑǼ வ߻ѝा΋࿶ၸҬεߐαǴ൩཮᝺ளٗࢂബ೷คज़ёૈ‫ޕޑ‬᛽ဃӦǴ ёૈளΠ፸ηωૈԖ۩ᗌΕԜಷ༜Ǵགྷό‫ډ‬౜ӧ‫ך‬ςֹԋ೭ҁፕЎྗ ഢ፯рਠ༜Ƕ २ӃߚதགᖴࡰᏤ௲௤‫ۏ‬ቼ‫ے‬ԴৣǴவεᏢਔ൩ుϪག‫ډڙ‬Դ ৣ௲Ꮲ‫ޑ‬዗‫ו‬ᆶҔЈǴӆ࿶ၸ೭‫ٿ‬ԃٰ‫ޑ‬ԸᔶҞࢉǵࡾ॥ϯ‫ػ‬ϐΠǴ όՠֹԋΑჴբᆶ౛ፕঋഢ‫ޑ‬ፕЎǴΨᏢಞ‫ډ‬ӵՖय़ჹୢᚒǵගр፾ ྽‫ޑ‬ჹ฼Ƕӧ೭ࢤය໔ǴԴৣ൩Ⴝ॥ᜦύ‫ܴޑ‬ᐩЇሦ๱‫ॺך‬ი໗Ǵӧ Ԝ᝘΢നଯ‫ޑ‬ལཀǶӧਠ༜‫ޑ‬നࡕ΋‫”א‬౥཰α၂”ύǴࡐᄪ۩ૈᗎፎ ‫ډ‬၏੻Ϙ௲௤ǵ೾Ϙ଄௲௤аϷ݅‫ے‬፣௲௤ǴӧԭԆϐύᗋૈኘ‫ୖޜ‬ у‫ޑך‬α၂Ǵ٠๏ϒࡐӭᝊ຦‫ޑ‬ཀ‫ـ‬ᡣፕЎ‫ֹࣁ׳‬๓ǶӚՏ௲௤ගឫ Ꮲғ‫ޑ‬ЈཀؒᏁᜤ‫ב‬Ƕ ௗΠٰाགᖴ‫ࢂޑ‬918ჴᡍ࠻‫ޑ‬ፏϦॺǶ‫ے‬ᑣεৣлࣁჴᡍ࠻໒ ᛒ‫ܗ‬βǴᡣ‫ॺך‬Ԗ๤፾‫ޜޑ‬໔ёа଺ࣴ‫ز‬ǹࣔሺᏢ‫ۊ‬ග‫”ॺךٮ‬λऍ ‫ޑ‬༰”ᎦᚑຽࠔǴᡣ‫ॺך‬Ԗӳ਻Յǹനᝄख़‫ޑ‬൩ࢂဃণ୚Ǵӵ݀ؒԖ д‫ޑ‬LVS೭ҁፕЎ൩཮΋୴Open Shortႝၡ୚ǼǹᗋԖӕఊ‫ޑ‬Ꮿ϶ ॺǺMixer៥ΓᐛֻǵMarchand៥ΓඵഩǴؒԖգॺ‫࡭ןޑ‬൩ค‫ݤ‬ዖ ‫ډ‬ԜਔԜ‫څ‬ǹᏢ‫ॺ׌‬Ǻৎֻǵम݇ǵᐇᗈǵയЎǴ΋ଆѺ೷፵ྦྷ‫ޑ‬918 ЦරփǶ നࡕགᖴ‫ޑך‬Рᒃǵ҆ᒃǵ‫ۂۂ‬ǵߓդаϷᜢЈ‫ޑך‬ໂᒃРԴǴ ‫עך‬೭ҁ౥཰ፕЎ‫ޑ‬ᄪᝬ᝘๏εৎǴா‫ޑ‬Ѝ࡭ࢂ‫߻ך‬຾‫୏ޑ‬ΚࢨྍǶ iii.

(7) Ҟᒵ ᄔाȐύЎȑ………………………………………………………………………..…i ᄔाȐमЎȑ…………………………………………………………………………ii ठᖴ………………………………………………………………………………….. iii Ҟᒵ ………………………………………………………………………………….iv კҞᒵ ………………………………………………………………………………vii ߄Ҟᒵ……………………………………………………..……………..…….……xiii ಃ΋ക ᆣፕ…………………………………………………………………… …….1 1.1 ߻‫…… ……………………………………………………………………ق‬.2 1.2 ፕЎᙁϟ……………………………………………………………………..2 ಃΒക ଯೲନᓎႝၡ………………………………………………………………..3 2.1 ߻‫…………………………………………………………………………ق‬..4 2.2 ୷ҁ PLL ၮբཷ‫……………ۺ‬....…………………………………………..4 2.2.1 PLL ӧௗԏᐒ΢‫ޑ‬ၮҔ………………………...……………...…...6 2.2.2 PLL ‫ ޑ‬Building Blocks Ϸ୷ҁၮբኳԄ……………………...…...7 2.3 RF ‫س‬಍ύ Synthesizer ‫ࢎޑ‬ᄬ………………………………………………8 2.3.1 Integer-N ‫ ޑ‬Synthesizer…..……………………………………..….8 2.3.2 Fractional-N ‫ ޑ‬Synthesizer………………………………………….9 2.4 ନ N/N+1 prescaler ϐ೛ी…………………………………………………10 2.4.1 ନ 2 ନ 3 ᚈኳନᓎᏔ…..………………………………………..….10 2.4.2 Swallow Counter ϐ೛ी………………………………………/….14 2.4.3 ӕ‫؁‬ᚈኳନᓎᏔᆶߚӕ‫ൂ؁‬ኳନᓎᏔ‫่ޑ‬ӝ…………………/!15 2.4.4 Multi-Modulus prescaler ϐ೛ी…………………………………..17 2.4.5 ‫ ٿ‬dual-modulus ନᓎᏔϐ่ӝ………..……………...………..….18 2.5 ჴբ΋Ǵ4/5 Dual-Modulus Prescaler (GaAs HBT 2͔m)…………………20 2.5.1 ࣴ‫୏ز‬ᐒ…………..…..………………………………………..….20 2.5.2 ࢎᄬϟಏ…………..…..………………………………………..….20 2.5.3 Ⴃीೕ਱ӈ߄……..…..………………………………………..….23 2.5.4 ჴෳ่݀……..…..……………………………………………..….23 2.5.5 ่ፕᆶ૸ፕ……...……………………………………………..…..26 2.6 ଯೲନΒႝၡ‫ޑ‬ၮҔᆶচ౛………………………………………………27 2.6.1 ନ 3 ႝၡࢎᄬᙁϟ……………………………………………..….27 iv.

(8) 2.6.2 Emitter-Coupled Inverter ϐႝၡ੝‫…………………܄‬...……..….29 2.6.3 ECL ϐຼᜐႝၡ…………………….…………………...……..….31 2.7ჴբΒǴStatic Frequency Divider (GaAs HBT 2͔m)……………………34 2.7.1 ࣴ‫୏ز‬ᐒ…………..…..………………………………………..….34 2.7.2 ࢎᄬϟಏ…………..…..………………………………………..….34 2.7.3 Ⴃीೕ਱ӈ߄……..…..………………………………………..….36 2.7.4 ჴෳ่݀……..…..……………………………………………..….37 2.7.5 ่ፕᆶ૸ፕ……...……………………………………………..…..39 2.8ჴբΟǴDynamic Frequency Divider (GaAs HBT 2͔m)…………...……40 2.8.1 ࣴ‫୏ز‬ᐒ…………..…..………………………………………..….40 2.8.2 ࢎᄬϟಏ…………..…..………………………………………..….40 2.8.3 Ⴃीೕ਱ӈ߄……..…..………………………………………..….45 2.8.4 ჴෳ่݀……..…..……………………………………………..….45 2.8.5 ่ፕᆶ૸ፕ……...……………………………………………..…..46 2.9ჴբѤǴSuperdynamic Frequency Divider (GaAs HBT 2͔m)……………47 2.9.1 ࢎᄬϟಏ…………..…..………………………………………..….47 2.9.2 Ⴃीೕ਱ӈ߄……..…..………………………………………..….48 2.9.3 ჴෳ่݀……..………..………………………………………..….49 2.9.4 ่ፕᆶ૸ፕ……....……………………………………………..….50 2.10ჴբϖǴInjection-locked Frequency Divider (GaAs HBT 2͔m)…...……51 2.10.1 ࣴ‫୏ز‬ᐒ………..…..…………………………………..……..….51 2.10.2 ࢎᄬϟಏ………..…..……………………………………..…..….51 2.10.3 Ⴃीೕ਱ӈ߄……..…..…………………………………..…..….56 2.10.4 ჴෳ่݀……..………………………………………………..….56 2.10.5 ่ፕᆶ૸ፕ……...…………………………………………....…..58 2.11ჴբϤǴRegenrative Frequency Divider (GaAs HBT 2͔m)…..…...……60 2.11.1 ࣴ‫୏ز‬ᐒ………..…..…………………………………..……..…..60 2.11.2 ࢎᄬϟಏ………..…..………………………………….…..…..….60 2.11.3 Ⴃीೕ਱ӈ߄……..…..…………………………………..…..…..63 2.11.4 ჴෳ่݀……..………………………………………………..…..64 2.11.5 ่ፕᆶ૸ፕ……...…………………………………………....…...65 2.12ჴբΎǴRegenrative Frequency Divider (SiGe HBT 0.35͔m)……...……67 2.12.1 Ⴃीೕ਱ӈ߄…..…..…………………………………..…..…….67 2.12.2 ჴෳ่݀…..……………………………...…………………..…..68 2.12.3 ่ፕᆶ૸ፕ…...…………………...………………………....…...70 v.

(9) 2.13ჴբନΒႝၡϐ੝‫܄‬Кၨ…………………………………//……...……71 ಃΟക ጠӝႝགᓸ௓ਁᕏᏔ………………………………………………………72 3.1 ߻‫…………………………………………………………………………ق‬73 3.2 ୷ҁচ౛Ϸႝၡࢎᄬ………………………………………………………73 3.2.1 ୷ҁচ౛…………………………………………………………….73 3.2.2 ೏୏ߔ‫ל‬ᙯඤ……………………………………………………….77 3.2.3 LC-tank ϐ฻ਏႝၡ………………………………………………...80 3.3 LC ᓸ௓ਁᕏᏔϐ೛ीୖኧന٫ϯ…..……………………………………80 3.3.1 LC аϷႝ඲ᡏϐᒧҔచҹ…………………..…………………….80 3.4 Phase Noise…………………………………………………………………81 3.4.1 Ֆᒏ Phase Noise…………………………………………………….81 3.4.2 Q ॶჹ Phase Noise ‫ޑ‬ቹៜ………………………………………….83 3.4.3 Phase Noise ӧ VCO ‫ޑ‬ౢғᐒ‫…………………ڋ‬..……………….85 3.4.3 VCO ‫ୃޑ‬ᓸႝࢬჹ Phase Noise ‫ޑ‬ቹៜ……………..…………….89 3.5 Pulling Ϸ Pushing ౜ຝ………..……………………………………………91 3.6 ৡ୏ Bipolar LC Oscillator…….……………………………………………92 3.7 ჴբ΋ǴVoltage-Controlled Oscillator with Differential Excitation Trifilar (SiGe HBT 0.35͔m)……………………………………………...…………………95 3.7.1 ࣴ‫୏ز‬ᐒ………..…..…………………………………..……..…..95 3.7.2 ࢎᄬϟಏ………..…..………………………………….…..…..….95 3.7.3 Ⴃीೕ਱ӈ߄……..…..……………………………...…..…..…..103 3.8 ჴբΒǴTrifilar Based Voltage-Controlled Oscillator (SiGe HBT 0.35͔m)……………………………………………...…………………………….104 3.8.1 Ⴃीೕ਱ӈ߄……..…..……………………………...…..…..…..104 ಃѤക ҅Ҭ࣬Տᓸ௓ਁᕏᏔ……………………………………………..………105 4.1 ߻‫………………………………………………………………………ق‬..106 4.2 Homodyne Receivers……………………………………………………...106 4.2.1 Homodyne ௗԏᐒ‫ޑ‬੝‫܄‬ᙁϟ…………………………………….106 4.2.2 а Homodyne ࣁ୷ᘵ‫ ޑ‬Image-reject ௗԏᐒ……………………...111 4.3 ӵՖౢғ҅Ҭ࣬Տૻဦ….....……………………………………………114 4.3.1 ΋૓໺಍‫҅ޑ‬Ҭ࣬ՏౢғБ‫……………………………………ݤ‬114 4.3.2 ճҔ VCO ጠӝౢғ҅Ҭ࣬Տ‫ ޑ‬LO………………………………117 (1) Parallel QVCO…………………………………………………117 (2) Parallel with phase shift QVCO………..………………...……121 (3) Top-Series Quadrature VCO...…………………………………123 (4) Buttom-Series Quadrature VCO...………………..……………132 (5) Superharmonic Coupling QVCO...……...………..……………133 4.4 ჴբ΋ǴQuadrature VCO Using Top-Series Coupling Structure (GaAs HBT vi.

(10) 2͔m)…………………..…………………………………………………...………128 4.4.1 Ⴃीೕ਱ӈ߄……………………………………………………...129 4.4.2 ჴෳ่݀…………………………………………………………...130 4.4.3 ่ፕᆶ૸ፕ………………………………………………………...131 4.5 ჴբΒǴQuadrature VCO Using Superharmonic Coupling (GaAs HBT 2͔m)……………………………………………………………………………….134 4.5.1 Ⴃीೕ਱ӈ߄……………………………………………………...137 4.5.2 ჴෳ่݀…………………………………………………………...137 4.5.3 ่ፕᆶ૸ፕ………………………………………………………...138 4.6 ჴբΟǴQuadrature VCO Using Superharmonic Coupling (SiGe HBT 0.35͔m)………………………………………………………………………...….140 4.6.1 Ⴃीೕ਱ӈ߄……………………………………………………...141 4.6.2 ჴෳ่݀…………………………………………………………...142 4.6.3 ่ፕᆶ૸ፕ………………………………………………………...143 ಃϖക ่ፕ……………………..…………………………………………………146 ୖԵЎ᝘……………………………………………………………………………149. vii.

(11) კҞᒵ კ 2.1. Synthesizer ӧԏวᐒ΢‫ޑ‬ᔈҔ………………………………….…………5. კ 2.2 Spur ჹௗԏૻဦ‫ޑ‬ቹៜ……………………………………………………5 კ 2.3 Locking time ཀҢკ………………………………...………………………6 კ 2.4. ‫ׯ‬ᡂᒡрᓎ౗ٰঅ҅࣬Տৡ………………………………………………7. კ 2.5. ୷ҁ‫ ޑ‬PLL ࢎᄬ……………………………………………………………8. კ 2.6 Integer-N Synthesizer………………………………….……………………8 კ 2.7. Fractional-N ‫ޑ‬ౢғБԄ...…………………………………………………9. კ 2.8. Fractional-N Synthesizer…………………………………………..………10. კ 2.9. Example of Fractional-N Synthesizer………….………………………….10. კ 2.10 ନ 4 ᡄᒠႝၡკ………………………………………………..…………..11 კ 2.11 ନ2ନ3ϐႝၡკ…………………………………………………………..13 კ 2.12 ନ2ନ3ႝၡϐਔᡂკ……………………………………………..………13 კ 2.13 όӕௗጕ೛ी‫ޑ‬ନ2ନ3ႝၡ………..……………………………………14 კ 2.14 ཥԄନ2ନ3ႝၡϐਔᡂკ………………………………………………..14 კ 2.15 ନ16~31ᡄᒠႝၡკ………………………………………………………15 კ 2.16 ନ16~31ႝၡϐਔᡂკ……………………………………………………15 კ 2.17 ନ15ନ16ᡄᒠႝၡკ……………..………………………………………16 კ 2.18 ନ15ନ16ႝၡϐਔᡂკ……………..……..……..………………………16 კ 2.19 ନ64~79ᡄᒠႝၡკ……………..………....……..………………………17 კ 2.20 ନ64~79ႝၡϐਔᡂკ…………..………....……..………………………18 კ 2.21. ÷2/3ႝၡ(όҔ(0,0)‫ރ‬ᄊ)…..………....……..……….……………….…18. viii.

(12) კ 2.22. ÷2/3ႝၡϐਔᡂკ………….………....…..…………………….…….…19. კ 2.23. ÷4/5ႝၡ…………………….……....……..……………………….….…19. კ 2.24. ÷4/5ႝၡ÷4/5ႝၡϐਔᡂკ……..…....……..…………………….….…19. კ 2.25. ÷22/23ᡄᒠႝၡკ…………………..…....…..……………………….…19. კ 2.26. ÷22/23ႝၡϐਔᡂკ………………..…....…..……………………….…19. კ 2.27. ø4/5ᡄᒠႝၡკ……………………..…....…..……………………….…20. კ 2.28 ‫ٳ‬ΕNAND gate‫ޑ‬ø4/5ႝၡ………..…....……..……………………….…21 კ 2.29 ‫ٳ‬ΕNAND gate‫ޑ‬DFF………..……………………….……………….…21 კ 2.30 ߻࿼ᒡΕભႝၡ………..………………...…………….……………….…22 კ 2.31 ᒡр጗ፂભႝၡ………..………………...…………….……………….…23 კ 2.32 ନ2ႝၡӧSynthesizer΢‫ޑ‬ၮҔ……...…………………..…………….…27 კ 2.33. D-latch ಔԋ‫ ޑ‬DFF…………………………………………………….…28. კ 2.34 ൂ΋D-latch‫ޑ‬ႝၡკ...…..……………………………….…………….…28 კ 2.35 ჴሞ٬Ҕ‫ޑ‬D-latchႝၡკ…….………………………….…………….…29 კ 2.36 ኳᔕECL Inverter੝‫ޑ܄‬ႝၡკ...…..….……………….………..…….…30 კ 2.37 ECL Inverter‫ޑ‬ᒡрᡂϯკ...…..….………………....…….………….…30 კ 2.38 ႝࢬྍႝၡკ...…..….………………...…….………………………….…32 კ 2.39. Emitter Followerႝၡკ...…..…..……...…….……….……………….…32. კ 2.40 ৡ୏‫ޑ‬clockౢғᏔ…….....…..……...…….…………..……………….…33 კ 2.41 ৡ୏‫ޑ‬ECL Inverter……......…..……...…….……….………………….…33 კ 2.42 Divide-by-2 black diagram….…..……...…….…….….……………….…34 კ 2.43 D-Latch Schematic………….…..……..…….…….…..……………….…35 კ 2.44 ୏ᄊନᓎႝၡϐҢཀკ…….…....…...…….……….………………….…40 კ 2.45. Differential Clock‫ޑ‬ౢғБԄ…….…..…….…….….…………….….…41. კ 2.46. Static DFF…………………………..…….……….…..…………….….…42. კ 2.47. Dynamic DFF……………………......…….……….……………….….…42 ix.

(13) კ 2.48 ୏ᄊନᓎᏔ‫ޑ‬λૻဦ฻ਏႝၡ (a) clock = high (b) clock = low….....…43 კ 2.49. StaticᆶDynamic‫ޑ‬timing diagram…..…….………..…….…….….….…44. კ 2.50. Super-dynamic D-FF circuit….…..……...………….……..….…….….…48. კ 2.51. Super-dynamic output waveform….…..……...…….……..….…….….…48. კ 2.52. Free running VCO….…..……...…….…..………….………….…………52. კ 2.53. Injection-locked VCO….……...…….…..………….……….……………52. კ 2.54. ø2ࡕ‫ޑ‬noise transfer function. Emitter Followerႝၡკ…..……….……53. კ 2.55. ILFDϐႝၡკ….……...…….…..………….…………………….……...54. კ 2.56 ‫ޔ‬ጠӝႝགϐlayoutკ….……....…………….…………………………...55 კ 2.57 RFDϐBlock Diagram….……....……….….……………………...……...61 კ 2.58 RFD‫ޑ‬եᓎᏹբज़‫…ڋ‬.……....…………...………….……………........61 კ 2.59 RFDϐinput bufferϷਡЈႝၡკ….……....…………………….…........62 კ 2.60. Cherry-Hooper Amplifierϐimpedance mismatch….……....….……........62. კ 2.61. Inductor peakingϐᒡр጗ፂભ..................................................................67. კ 3.1 ӣ௤ႝၡϐҢཀკ………………………………………………………….73 კ 3.2 ਁᕏᏔϐཱུᗺӧፄኧѳय़΢‫ޑ‬ᡂ୏……..………………………………...74 კ 3.3 ਁᕏᏔϐ Nyquist Plot……………………………………………………....75 კ 3.4 ਁᕏᏔϐ one port ϸ৔‫س‬಍……………….………………………………..76 კ 3.5 კ 3.4 ϐૻဦࢬ୏კ……………………….……………..…………………76 კ 3.6 ਁᕏᏔϐ one port ॄႝߔ‫س‬಍…..………...………………………………..77 კ 3.7 Սᖄ RC ᆶ٠ᖄ RC ϐᙯඤ……………….…………………………….…..78 კ 3.8 Սᖄ LR ᆶ٠ᖄ LR ϐᙯඤ…………………………………..…...…….…..79 კ 3.9 ႝ৒Ԅߔ‫ל‬ᙯඤႝၡ……………………..…………………………….…..79 კ 3.10 ႝགԄߔ‫ל‬ᙯඤႝၡ………………………...………………………….....79 კ 3.11 LC-tank ϐ฻ਏႝၡᙯඤ……….…………………………….………….80 კ 3.12 VCO ᒡр‫ޑ‬౛གྷϷჴሞᓎ᛼……..……………………….…………….82 x.

(14) კ 3.13. Phase Noise ‫ޑ‬ीᆉБ‫…………………………………………………ݤ‬.82. კ 3.14 ဵᘍਏᔈჹᎃ߈ௗԏૻဦ‫ޑ‬ቹៜ……..……………………………….....83 კ 3.15 ဵᘍਏᔈჹ QPSK ‫ޑ‬ቹៜ……………………..…………………………….83 კ 3.16. LC-tank ϐ band-pass ਏᔈ……………………………………………….84. კ 3.17. LC-tank ໒଑ၡϐႝၡკ…………….………………………………….84. კ 3.18. Q=50 ᆶ Q=10 ϐ LC-tank ࣬Տᡂϯკ………………….……………….85. კ 3.19 Noise җഈ଑ၡ‫ޑ‬΋ᗺ‫ݙ‬Ε……….…………………………….……….85 კ 3.20. 3-12 Ԅӧᓎ᛼΢‫ޑ‬ៜᔈ....…...………………………………….……….86. კ 3.21. Leeson’s equation ӧᓎ᛼΢‫ޑ‬ៜᔈ…………………………….………..87. კ 3.22 Noise җ Vtune ᆄ‫ݙ‬Ε……………………………………………………..88 კ 3.23 ۰‫ ݢ‬Noise җ Vtune ᆄ‫ݙ‬Εӧᓎ᛼΢‫ޑ‬ਏᔈ………………………...…….88 კ 3.24 ஒኧঁ VCO ‫ޑ‬ᒡруᕴ….…………………………………...………….90 კ 3.25 VCO ϐ Injection Pulling ౜ຝ……………………………...…………….91 კ 3.26 ଯф౗υᘋჹ VCO ‫ޑ‬ቹៜၡ৩……….………...……………………….91 კ 3.27 ൂ΋ transistor ϐ VCO ௗጕკ…………………………………………….93 კ 3.28 კ 3.27 ϐ‫ׯ‬຾ VCO ႝၡ………………….……………………………....93 კ 3.29. Colpitts ᆶ Hartley ϐ VCO ࢎᄬკ……...……………………………….93. კ 3.30 ճҔ active buffer ౢғߔ‫ל‬ᙯඤ..................................................................94 კ 3.31 ৡ୏ LC ਁᕏᏔ…………………………………………………………….94 კ 3.32 ճҔ cross-coupled pair ౢғॄႝߔ……………………………...……….94 კ 3.33 ‫ޔ‬ௗӣ௤ࢎᄬ……………………………………………………………...96 კ 3.34 ႝ৒ጠӝӣ௤………………………………..…………………………….96 კ 3.35 ႝགጠӝӣ௤………………………………………………………...…....97 კ 3.36 Varactor ୃᓸႝၡϷӣ௤ႝၡϐ่ӝ…………………………..……….98 კ 3.37 Colpitts VCO………………….……………………………….………….99 კ 3.38 Hartley VCO………………………..………………………….………….99 xi.

(15) კ 3.39 ճҔ transformer բߔ‫ל‬ᙯඤ…………..………………………………….99 კ 3.40 კ 3.39 ϐ฻ਏႝၡ…………………………….………………………….99 კ 3.41 ҁჴբϐֹ᏾ VCO ႝၡკ……………………...………………………100 კ 3.42. 1-to-2 transformer Ңཀკ………………………….……………………100. კ 3.43 Trifilar ӧჴሞႝၡ٬Ҕϐጄ‫…………………ٯ‬.………………...…...100 კ 3.44. Trifilar ϐᙅጕБ‫……………ݤ‬.……………..…………………………101. კ 3.45 ճҔ Center-tape ٰჴ౜ Differential Trifilar…………………………….101 კ 4.1 Homodyne Receiver ………………………………….……...…………...107 კ 4.2 AM ૻဦ࿶ Homodyne ௗԏᐒϐफ़ᓎៜᔈ………………….………….107 კ 4.3 FM ૻဦ࿶ Homodyne ௗԏᐒϐफ़ᓎៜᔈ……………………..……….107 კ 4.4 ҅Ҭ࣬Տௗԏᐒ…………………………………………………………...107 კ 4.5 FM ૻဦ࿶҅Ҭ࣬Տௗԏᐒϐफ़ᓎៜᔈ………….……………….…….108 კ 4.6 LO ૻဦ೷ԋ‫ ޑ‬Self-mixing…………..…………………………….……108 კ 4.7 RF ૻဦ೷ԋ‫ ޑ‬Self-mixing………………………………………………109 კ 4.8. I/Q mismatch ӧԏวᐒ΢‫ޑ‬ቹៜ…...……………………………………109. კ 4.9. I/Q mismatch ჹૻဦ০኱კౢғ‫ޑ‬ቹៜ……..………………………….110. კ 4.10 Even-order distortion…………………...………………………………..111 კ 4.11 Hartley ௗԏᐒύᓎ᛼‫ޑ‬ᡂϯ…………..……………………………….112 კ 4.12. Phase shifter ӧᓎ᛼΢‫ޑ‬ៜᔈ………..…………………………………113. კ 4.13 ճҔ೏୏ϡҹౢғ 90 ࡋ࣬Տৡ…………………………………………113 კ 4.14. Weaver ௗԏᐒύᓎ᛼‫ޑ‬ᡂϯ…………………………..………………114. კ 4.15. ճҔø2 ႝၡౢғ I/Q ૻဦ……...……………………………………….115. კ 4.16. ճҔ Poly-phase Filter ౢғ I/Q ૻဦ……………..……………………..116. კ 4.17. ҅Ҭ࣬ՏਁᕏᏔϐௗጕБԄ…………………...………………………116. კ 4.18. N ભ‫ ޑ‬Ring Oscillator…………...………………………………………116. კ 4.19 Parallel QVCO………………...…………………………………………117 xii.

(16) კ 4.20 PQVCO ϐႝࢬᆶႝᓸ࣬Տკ………….………………………………118 კ 4.21 PQvco ‫ޑ‬ጕ‫܄‬ኳࠠ………………………………………………………118 კ 4.22 Parallel QVCO ϐѤᅿᏹբ‫ރ‬ᄊ………..………………………………120 კ 4.23. ࢬ຾ LC-tank ‫ޑ‬ႝࢬໆ߄………………………………………………120. კ 4.24 PQVCO with Phase Shifter ϐጕ‫܄‬ኳࠠ………...………………………122 კ 4.25. ‫ٿ‬ᅿ Phase Shifter ϐႝၡკ…………….………………………………122. კ 4.26. Top-Series QVCO……………………….………………………………123. კ 4.27. Top-Series QVCO ϐ฻ਏъႝၡ……….………………………………124. კ 4.28 Top-Series QVCO ϐѤᅿᏹբ‫ރ‬ᄊ….…………………………………125 კ 4.29. ࢬ຾ LC-tank ‫ޑ‬ႝࢬໆ߄…….…………………………………………125. კ 4.30. კ 4.23c ‫ޑ‬ᚇૻྍаϷࢬ຾ LC-tank ‫ޑ‬ႝࢬໆ߄……………...………127. კ 4.31. ӧკ 4.28bǵd ‫ޑ‬ᚇૻྍаϷࢬ຾ LC-tank ‫ޑ‬ႝࢬໆ߄………………127. კ 4.32. Top-series QVCO ϐႝၡკ…………………………………….………128. კ 4.33. Symmetric Transformer ϐ Layout………...…………………….………129. კ 4.34 Fitted model………………………..…………………………….………129 კ 4.35. Transformer ϐໆෳ่݀…………………..…………………….………129. კ 4.36. Bottom-series QVCO ϐႝၡკ…….……..…………………….………132. კ 4.37. Superharmonic coupling QVCO ϐҢཀკ…….….…………….………134. კ 4.38. Superharmonic coupling QVCO ϐႝၡკ…….….…………….………135. კ 4.39. Symmetric Transformer Layout…….……………..…………….………135. კ 4.40 (a)VCO without current source filter (b)VCO with current source filter…………….………………...………136 კ 4.41. Superharmonic coupling QVCO ϐႝၡკ…….……………….………140. xiii.

(17) ߄Ҟᒵ ߄ 2.1 DFF ‫ޑ‬ᐟว߄…………………………………………....................................11 ߄ 2.2 ନ 3 ႝၡύ DFF ‫ރޑ‬ᄊᡂඤ ………………………………………………...12 ߄ 2.3 ନ 3 ႝၡ‫ ޑ‬K-Map ……………………………………………………………12 ߄ 2.4 ჴբନΒႝၡϐКၨ…………………………………………………………71 ߄ 4.1 ჴբ҅Ҭ࣬ՏਁᕏᏔϐКၨ…………………………………………..……145. xiv.

(18) ಃ΋ക ᆣፕ. 1. ಃ΋ക ᆣፕ. 1.

(19) ಃ΋ക ᆣፕ. 2. 1.1 ߻‫ق‬ ႝη೯ߞਔжଆ‫ܭۈ‬1844ԃǴነථวܴΑԖጕႝൔࡕΓᜪωள аբߏຯᚆ‫ૻޑ‬৲໺ԏǶ‫ډ‬Α1859ԃǴଭёѭว৖рคጕႝൔǴԋ ࣁคጕႝ೯ૻ‫ޑ‬Ӄ០ǶኧΜԃࡕǴ‫ن‬ᅟ‫߈׳‬΋‫ޑ؁‬วܴႝ၉Ǵஒᖂ ‫ݢ‬ᙯඤԋႝࢬᡂϯӧᙖҗႝጕ໺ሀǶ౜ӧ‫ࡐޑ‬දϷ‫ޑ‬ЋᐒǴόၸࢂ ᙖคጕႝ໺ଌႝ၉‫ૻޑ‬ဦǶႝ඲ᡏวܴࡕǴคጕ೯ૻ‫ࢂ׳‬΋ВίٚǴ у΢ႝတ‫ೌמ‬຾‫؁‬ǵፁࢃᆶӀᠼ‫ޑ‬ၮҔǴ೷ԋҞ߻྽आ‫ޑ‬คጕ೯ૻ ౢ཰Ƕคጕ೯ૻ‫߻ޑ‬ᆄႝၡࢂ᏾ঁ‫س‬಍ႝၡ‫ޑ‬౟ᓍǴѸ໪ஒ୷ᓎૻ ဦуаፓᡂว৔‫ډ‬ௗԏᆄǴය໔ᗋѸ໪‫ܔל‬ᕉნ‫ޑ‬ӚᅿυᘋǴനࡕ ᗋளௗԏ‫ܫ‬εཱུλ‫ޑ‬ௗԏૻဦǴа‫୷ٮ‬ᓎႝၡೀ౛Ƕ߻ᆄ‫ޑ‬ႝၡ೛ ीѸ໪Եቾ‫׳‬ӭ‫ޑ‬೛ीӢનǴόӕ‫ܭ‬ᜪКႝၡ೛ीǴջ٬բΑ Layout ΢஌ғਏᔈ‫ޑ‬ᆐ‫ڗ‬Ǵ٠όૈߥ᛾ႝၡ‫҅ޑ‬ԋၮբǶӧႝ඲ᡏ‫ ޑ‬fitting model ΢Ǵӵ݀ѝൂપ fit IV curve ό‫ى‬аၮҔӧ RF ೛ीǴႝၡ‫ޑ‬ᓎ ౗ຫଯຫሡाፄᚇ‫ޑ‬฻ਏႝၡٰඔॊႝ඲ᡏ੝‫܄‬Ǵ೛ी֚ᜤࡋߡග ϲኧ७ǶࣗԿӧૻဦ‫وޑ‬ጕǵႝ৒ႝག‫ޑ‬ኳᔕ೿໪࿶ၸ EM Tool ‫ޑ‬ ՗ෳǴаխଯᓎૻဦጠӝวණ‫ځ܈݈୷ډ‬дϟ፦ύǶ. 1.2 ፕЎᙁϟ ҁፕЎϩࣁϖঁക࿯Ǵಃ΋ക࿯ࣁ‫ׇ‬ፕǴᇥܴคጕ೯ૻ‫ޑ‬ว৖ ᆶ߻ᆄႝၡ‫ޑ‬೛ीᢀ‫ۺ‬ǹಃΒകஒϟಏӚᅿଯೲନᓎႝၡ‫ࢎޑ‬ᄬа ϷၮҔ‫ޑ‬ਔᐒǹಃΟകϟಏਁᕏᏔ‫୷ޑ‬ᘵ౛ፕ‫ک‬ബཥ‫ਁޑ‬ᕏᏔ่ ᄬǹಃѤകϟಏ҅Ҭૻဦ‫ޑ‬Ҕ೼٠КၨӚࢎᄬ‫҅ޑ‬Ҭ࣬ՏਁᕏᏔ‫ޑ‬ ᓬલᗺǶಃΒ‫ډ‬ಃѤകନΑ౛ፕ΢‫ޑ‬ᇥܴѦǴᗋԖჴբ‫ޑ‬ໆෳ่݀ аբᡍ᛾Ƕಃϖക߾ჹ΢ॊ‫ޑ‬ჴբႝၡբ΋ᕴ่Ƕ. 2.

(20) ಃΒക ଯೲନᓎႝၡ. 3. ಃΒക ଯೲନᓎႝၡ. 3.

(21) ಃΒക ଯೲନᓎႝၡ. 4. 2.1 ߻‫ق‬ RFௗԏᐒύ‫܌‬Ҕ‫ޑډ‬VCO೯த཮൪Εӧᓎ౗ӝԋᏔύǴ٬ᒡр ᓎ ౗ ‫ྗ ࣁ ׳‬ዴ Ƕᓎ ౗ ӝ ԋ Ꮤӵ ݀ൂ Ҕ ᜪ К БԄ ٰჴ ౜ Ǵ ё ϩࣁ integer-N‫ک‬fractional-NࢎᄬǴBuilding BlockύࣣሡाନᓎᏔ(Prescaler ‫܈‬Frequency Divider)ٰஒVCOਁр‫ૻޑ‬ဦफ़ԿեᓎǴᆶҡमਁᕏᏔ‫܈‬ ‫ځ‬дྗዴࡋଯ‫ਁޑ‬ᕏૻဦբ࣬ՏКၨǶନᓎᏔ‫ޑ‬ႝၡ೛ीཷ‫ۺ‬ё٩ྣ ନኧ‫ޑ‬ӭჲբ୔ϩǺ(1)ӵ݀ाჴ౜ଯନኧ‫ޑ‬ନᓎᏔǴሡҔኧՏႝၡ΢ த‫ޑـ‬counter೛ीБԄǴճҔኧঁD-type Flip-Flop(DFF)଺ᡄᒠ‫ޑ‬௢ ᆉǴ൩ёа‫ޕ‬ၰӚDFF‫ޑ‬ௗጕБԄǶ(2)ӵ݀ନኧե(ࡰନΒႝၡ)Ǵӧ ႝၡ΢‫ޑ‬೛ीБԄ൩ԖࡐӭǺႽࢂStaticǵDynamicǵSuperdynamicǵ Injection LockedǵRegenerative฻ࢎᄬǴόӕࢎᄬԖঁձ‫ޑ‬ᓬલᗺǴё ٩‫س‬಍ሡ‫؃‬᏷΋٬ҔǶҁക‫ޑ‬ϣ৒ஒ௖૸΢ॊ‫ޑ‬ӚᅿନᓎᏔǴӧ౛ፕ ‫ک‬ჴբ΢೿Ԗᑞஏ‫ޑ‬ᇥܴǴග‫ٮ‬ҁჴᡍ࠻к‫ޑى‬ႝၡໆෳၗ਑Ǵஒٰ ёаၮҔӧᓎ౗ӝԋᏔύǶ. 2.2 ୷ҁPLLၮբཷ‫ۺ‬ 2.2.1 PLLӧԏวᐒ΢‫ޑ‬ᔈҔ ӧRFௗԏᐒ΢ਁᕏᏔ‫ޑ‬ᓎ౗Ѹ໪ࡐᛙ‫ۓ‬Ǵ٠Ъૈ୼λໆԶᆒྗ‫ޑ‬ ၢᓎǴӢࣁӧ΋૓‫ޑ‬คጕ೯ૻ‫س‬಍཮ा‫ਁ؃‬ᕏᓎ౗౽୏ኧΜkHzٰբ ௗ໺ૻဦ‫ޑ‬ᓎࢤϪඤǴ‫܌‬аѸ໪ॷख़Synthesizerֹٰԋ಄ӝ‫س‬಍ा‫؃‬ ‫ޑ‬ၢᓎ୏բǴࢎᄬӵკ2.1‫܌‬ҢǶ. 4.

(22) ಃΒക ଯೲନᓎႝၡ. 5. LNA. Duplexer Filter. Frequency. Channel. Synthesizer. Selection. PA. ʳ. კ2.1 Synthesizerӧԏวᐒ΢‫ޑ‬ᔈҔ ନΑ΢ॊ‫ޑ‬ा‫؃‬ѦǴ SynthesizerᗋሡाԵቾphase noiseǵspur (sideband)аϷlocking time (ᙹ‫ۓ‬ਔ໔)Ǵ೭٤Ӣન೿཮ቹៜௗԏᐒ‫ޑ‬੝ ‫܄‬Ƕ೯தൂᐱ‫ޑ‬VCOᒡрૻဦό཮ԖspurౢғǴόၸ࿼Ε‫ډ‬Synthesizer ࡕ൩཮Ԗspurр౜ǶSpurჹௗԏૻဦ‫ޑ‬ቹៜёаҗკ2.2ٰᇥܴǴ྽ synthesizer‫ޑ‬ᒡрନΑ͠MPѦᗋԖspurӧ͠TǴЪௗԏ‫ૻޑ‬ဦନΑ͠1ᗋ Ԗυᘋྍ͠jouǴу΢͠T.͠MPʳ>͠jou.͠1ᜢ߯ԋҥǴӧ͠MP‫͠ע‬1‫ૻޑ‬ဦफ़ ‫ډ‬IF band(͠JG)‫ޑ‬ӕਔ͠TΨ‫ע‬υᘋྍ͠jouफ़‫͠ډ‬JGǴ೷ԋૻဦ‫ޑ‬ཞ྄Ƕ ΋૓‫سޑ‬಍཮ा‫؃‬spurाКcarrierե60dBǴόฅ൩ࢂஒ͠T.͠MP‫ޑ‬໔႖ ᡂεǴᡣ͠jou‫ޑ‬υᘋྍёаҔduplexer‫܈‬bandpass filterٰ‫ڋ׭‬Ƕ Interferer Desired Signal RF Input. Z0. LO. Zint. Z. Sideband. Synthesizer Output. ZLO. ZS. Z. IF Output. Z. ZIF. კ2.2 Spurჹௗԏૻဦ‫ޑ‬ቹៜ Locking timeჹsynthesizerΨࢂ΋ঁख़ा‫ୖޑ‬ኧǴ྽channelᒧ᏷ 5.

(23) ಃΒക ଯೲନᓎႝၡ. 6. ႝၡ)კ2.1*ा‫؃‬synthesizerၢᓎ‫ډ‬ќ΋ঁchannelǴsynthesizerሡा΋ ‫ޑۓ‬ਔ໔ஒᒡрᓎ౗ፓ᏾‫ډ‬၀channel΢(კ2.3)Ǵlocking time൩ࢂ‫ۓ‬က ा ޸ ӭ Ͽ ਔ ໔ ω ૈ ᕇ ள ᛙ ‫ ۓ‬ᒡ р Ǵ ӧ fast frequency-hopped spread-spectrum systemԜୖኧЀ‫ځ‬ख़ाǶ٩ྣRF‫س‬಍‫ޑ‬όӕǴჹ locking time‫ޑ‬ा‫؃‬வኧΜms‫ډ‬ኧΜµsό฻Ƕ Lock Transient. Z2. Z1. t კ2.3 Locking timeҢཀკ. 2.2.2 PLL‫ޑ‬Building BlocksϷ୷ҁၮբኳԄ ΋ঁ౛གྷ‫ޑ‬VCOёаҔ Zout ZFR KVCOVcont ٰ߄Ң‫ځ‬ᒡрᓎ౗‫ޑ‬ ª. t. º. ᡂϯǴӧtime domain΢߾ࢂҔ y (t ) Ac cos«ZFR t KVCO ³ Vcont (t )dt » ߄ҢǶ ¬. f. ¼. ӧࣴ᠐PLLਔ೯தຎVCOࣁlinearЪtime-invariant‫سޑ‬಍ǴᒡΕૻဦ t. Wdpou཮ౢғ࣬Տᒡр Iout. KVCO ³ Vcont (t )dt Ǵӧfrequency domain΢‫ޑ‬ᒡΕ f. ᒡрᙯ౽‫ڄ‬ኧࣁǺ. ) out ( s) Vcont. KVCO ǶҗԜё‫ޕ‬ा‫ׯ‬ᡂᒡрૻဦ‫࣬ޑ‬ՏѸ s. ໪Ӄ‫ׯ‬ᡂᒡрૻဦ‫ޑ‬ᓎ౗຾Զᑈϩԋ࣬ՏǶ! аკ2.4ࣁ‫ٯ‬Ǻӧu=u1ਔਁᕏᓎ౗‫ୖک‬Եᓎ౗໔Ԗ٤೚࣬ՏৡǴ ࣁΑ෧Ͽ၀࣬ՏৡǴӧu>u1ਔWdpouቚу 'V ᡣਁᕏᓎ౗΢ϲǴਁᕏᓎ౗ ‫࣬ޑ‬Տಕᑈ൩཮КୖԵᓎ౗‫ז‬Ƕ྽࣬Տᇤৡफ़‫ډ‬႟ǴWdpou཮फ़ӣ‫ډ‬চ 6.

(24) ಃΒക ଯೲନᓎႝၡ. 7. ॶǴԜਔਁᕏૻဦᆶୖԵૻဦ‫ޑ‬ᓎ౗཮࣬ӕԶ࣬Տᇤৡ฻‫ܭ‬႟Ƕ࿶ၸ а΢‫ޑ‬ᇥܴёа‫ޕ‬ၰVCO‫ޑ‬ᒡр࣬ՏόૈൂҗҞ߻‫ޑ‬Wdpouॶٰ،‫ۓ‬Ǵ Ѹ໪ᢀჸ΋ࢤWdpouჹਔ໔‫ޑ‬ᡂϯωૈ‫ޕ‬ၰǶ. Reference. Vcont VCO Output. t0. t1. t. კ2.4 ‫ׯ‬ᡂᒡрᓎ౗ٰঅ҅࣬Տৡ ΋ঁ౛གྷ‫ޑ‬phase detector(࣬ՏୀෳᏔ)ёаஒ‫ڬঁٿ‬යૻဦ‫࣬ޑ‬ ՏৡᙯඤԋdcॶᒡрǺ Vout. K PD 'I ǴWpvu ࣁᒡрႝᓸǹ K PD ࣁphase. detector‫ޑ‬ቚ੻(V/rad)Ǵ 'I ࣁ‫ڬٿ‬යૻဦ‫࣬ޑ‬ՏৡǶ ᙹ࣬଑ၡࢂаphase errorࣁКၨ୷ᘵ‫ޑ‬ӣ௤‫س‬಍(კ2.5)ǴѬх֖΋ ঁphase detectorǵlow-pass filterаϷVCOǶPhase detectorࢂ΋ঁᇤৡ ‫ܫ‬εᏔǴᡣ x (t ) ‫ ک‬y (t ) ໔‫ޑ‬phase error( 'I )ӧࡐλΑਔং൩ё೏ୀෳ рǶ྽ 'I όӆᒿਔ໔ᡂϯǴԜਔ൩ёаᆀϐᙹ‫ރۓ‬ᄊ)locked)Ƕ. x (t ). Loop Filter. Phase Detector. y (t ). Volltage Controlled Oscillator. ʳ. კ2.5 ୷ҁ‫ޑ‬PLLࢎᄬ 7.

(25) ಃΒക ଯೲନᓎႝၡ. 8. ӧ locked ‫ ޑ‬௃ ‫ ݩ‬Π Ǵ ‫ ܌‬Ԗ ‫ ૻ ޑ‬ဦ ӧ ଑ ၡ ύ ೿ ၲ ‫ ډ‬ᛙ ᄊ (steady state)ǶPLL‫؁ۓᙹޑ‬ᡯӵΠǺphase detectorᒡр҅К‫ܭ‬phase error( 'I ) ‫ޑ‬dcॶǴlow-pass filter߾ࢂஒphase detector‫ޑ‬ଯᓎૻဦᘠ௞Ǵஒdcૻ ဦ໺ଌ‫ډ‬VCO‫ޑ‬ᓎ౗௓‫ڋ‬ᆄǴፓ᏾ᒡрᓎ౗‫ޑ‬ଯեǶ. 2.3 RF‫س‬಍ύSynthesizer‫ࢎޑ‬ᄬ 2.3.1 Integer-N‫ޑ‬Synthesizer PFD. f RFF. Divider M f out. f out. VCO. Loop Filter. M f REF. კ2.6 Integer-N Synthesizer Ԝࢎᄬ‫ޑ‬ᓎ౗ᒡрёҔ f out. f 0 kf ch ٰ߄ҢǴg1ࢂಃ΋ঁdiboofm. ‫ޑ‬ᓎ౗ǴgdiࢂΠ΋ঁdiboofm໔ຯǶԜၢᓎБ‫ݤ‬ሡҔ‫ډ‬ёፓନኧ‫ޑ‬ନ ᓎᏔǶҗკ2.6ёаౢғ f out. Mf REF ‫ޑ‬७ᓎਏ݀ǴԶMёҗനλॶML‫؂‬. ԛቚу΋Ǵ΋‫ډޔ‬നεॶMHǶௗΠٰ൩ёаᙖ΢ॊ‫ঁٿޑ‬฻Ԅٰ، ‫ۓ‬channel‫ޑ‬໔႖Ǻ ଷ೛നե‫ޑ‬channel (ML)ӧ f 0 (k=0)Ш f out1 ಃΒchannel (ML+1)ӧ f 0 f ch (k=1) Ш f out 2 channel space൩฻‫ ܭ‬f out1 f out 2. f 0 kf ch. f 0 f ch. f0. M L f REF ǴԶ. M L 1

(26) f REF Ǵ‫܌‬а. f REF ШୖԵᓎ౗൩ࢂchannel spaceǶ. Ԝ ࢎ ᄬ ‫ ޑ‬લ ᗺ ൩ ࢂ Ԗ resolution ‫ ک‬bandwidth ‫ ޑ‬trade-off Ǻ ଯ 8.

(27) ಃΒക ଯೲନᓎႝၡ. 9. resolution ሡ ा ե ‫ ޑ‬f REF Ǵ ё ࢂ ा ଯ ‫ ޑ‬bandwidth ࠅ ሡ ा ଯ ‫ ޑ‬f REF Ƕ Fractional-N‫ࢎޑ‬ᄬ൩ࢂࣁΑ‫ׯ‬๓ԜલᗺԶ೛ीр‫ޑ‬Ƕ. 2.3.2 Fractional-N‫ޑ‬Synthesizer ӧinteger-N‫ޑ‬synthesizerύchannel spaces൩฻‫ୖܭ‬Եᓎ౗Ǵ೷ԋ loop bandwidthࡐλǴӵ݀‫ׯ‬Ҕfractional-N൩ёаᡣᒡрᓎ౗‫ޑ‬ᡂ୏ε λࢂୖԵᓎ౗‫ޑ‬ϩኧǴӢԜୖԵᓎ౗ёа೛ी‫ޑ‬Кchannel spaceεǴ loop bandwidthᒿϐගଯԶЪό཮ჹresolutionౢғቹៜǶௗΠٰҔკ 2.7ٰᇥܴfractional-N‫ޑ‬ౢғБ‫ݤ‬Ǻx(t)ࢂ΋ঁᓎ౗ࣁ f ‫ૻޑ‬ဦǴ y (t ) ߾ ࢂஒx(t)‫؂‬႖Tb൩‫ע‬΋ঁpulse౽ନǴ‫܌‬а y (t ) ӧ‫ঁ؂‬Tb໔཮Ԗ f u Tb 1 ঁpulseǴёа‫ע‬Ѭ‫ޑ‬ᓎ౗ຎࣁ f . 1 Ƕᙖҗ‫ׯ‬ᡂTb൩ёᡣᒡрᓎ౗բ Tb. λ‫؁‬໘౽୏Ƕ Pulse Re mover Input. x (t ). Pulse Re mover Output. y (t ). t. Tb. კ2.7 Fractional-N‫ޑ‬ౢғБԄ Ҟ߻ቶ‫ݱ‬٬Ҕ‫ޑ‬fractional-NࢎᄬӭҔdual-modulus prescalerٰ೛ ी(კ2.8)Ǵ‫ۺཷځ‬Ψࢂӧ‫ຼۓڰ‬යΠ౽ନ΋ঁpulseٰ‫ׯ‬ᡂѳ֡‫ޑ‬ନ ኧǶӵ݀modulus control‫ޑ‬ᒡΕ೛‫ࢂۓ‬ǺନᓎᏔ࿶ၸAঁନNᒡрࡕஒ ନኧᡂԋN+1ӆᆢ࡭BঁᒡрǴᒿջΞஒନኧख़೛ࣁNǴ٩ԜൻᕉΠ ѐǶനಖёளѳ֡ନኧࣁ. A u N B u N 1

(28) Ǵᒧ‫ڗ‬፾྽‫ޑ‬AǵBϷNॶࡕ A B. ൩ёа೛ीр‫܌‬ሡ‫ޑ‬ϩኧࠠନኧǶ 9.

(29) ಃΒക ଯೲନᓎႝၡ. 10. PD. Loop. f REF. Filter. f out. VCO. Pr escaler y n / n 1

(30) Modulus Control. კ2.8 Fractional-N Synthesizer аΠᖐঁᙁ‫ٯ‬Ǵ೛‫ ۓ‬f REF 1MHz ǵ N 10 Ǵკ2.9ᒧ᏷A=9ǵB=1Ǵ Ψ൩ࢂ࿶ၸ9ঁନ10‫ޑ‬ᒡрࡕModulus Controlբ‫ׯ‬ᡂǴᡣନኧᡂࣁ11 ‫܌‬аନᓎК‫ࣁٯ‬Ǻ. 9 u 10 1 10 1

(31) 9 1. 10.1 Ǵள‫ډ‬ᒡр‫ޑ‬ᓎ౗ࣁ10.1MHzǶ. PFD. LPF. f REF. f out. VCO. y 10 / 11 TREF. t 9TREF. y 10. კ2.9 Example of Fractional-N Synthesizer. 2.4 ନN/N+1 prescalerϐ೛ी 2.4.1 ନ2ନ3ᚈኳନᓎᏔ εӭኧ‫࣬ᙹޑ‬ᓎ౗ӝԋᏔ೿཮Ҕ‫ډ‬ଯೲᚈኳନᓎᏔǴԜႝၡёҔ ΋ঁ௓‫ૻڋ‬ဦٰ‫ׯ‬ᡂନኧελǶନ2ନ3ႝၡനࣁቶ‫ݱ‬٬Ҕ(კ2.10)Ǵ җ‫ܭ‬ø304ࢂനλ‫ޑ‬ᚈኳନኧǴѬ٬ҔനϿ‫ޑ‬ᡄᒠႝၡٰჴ౜Ǵӧೲࡋ ‫߄ޑ‬౜΢΋‫ۓ‬Кନ3ନ4‫ځ܈‬д‫׳‬ଯନኧ‫ޑ‬ନᓎႝၡٰ‫זޑ‬Ƕ΋ঁ 10.

(32) ಃΒക ଯೲନᓎႝၡ. 11. D-type‫ޑ‬flip-flop(DFF)ёаග‫ٮ‬2ঁtime delayǴ‫܌‬аჴ౜ନ2ନ3ႝၡ ሡा‫ঁٿ‬D-type‫ޑ‬flip-flopٰග‫ٮ‬3ঁа΢‫ޑ‬time delayǴନ3‫ޑ‬фૈω ૈၲ‫ډ‬Ƕკ3/21ႝၡ࿶தёаӧpaper΢࣮‫ډ‬ǴௗΠٰஒ૸ፕӵՖҔ ᡄᒠႝၡٰჴ౜Ƕ!. Q1 Q2. CLK. კ2.10 ନ4ᡄᒠႝၡკ ߄2.1ࢂDFF‫ޑ‬excitation tableǴҔٰᇥܴǺDж߄DFFᒡΕᆄ‫ޑ‬ኩ ӸૻဦǴTransitionж߄࿶ၸ΋ঁclk០୏DFFࡕ‫ޑ‬ᒡрૻဦᡂ୏Ƕҗ߄ ё‫ޕ‬DFF‫؂‬࿶ၸ΋ԛclk០୏Ǵ൩཮‫ע‬Dᆄ‫ૻޑ‬ဦ໺ଌ‫ډ‬QᆄǶ! Transition. D. 0 ʈ 0. 0. 0 ʈ 1. 1. 1 ʈ 0 1 ʈ 1. 0 1. ߄2.1 DFF‫ޑ‬ᐟว߄ ‫ޕ‬ၰDFF‫ޑ‬ᏹբኳԄࡕ൩ёаुр2-bit counter‫ޑ‬state table(߄ 2.2)Ƕ‫ঁٿ‬DFF‫ޑ‬ᒡрёаග‫ٮ‬4ঁstateǴϩձࢂ(Q1,Q2)=(0,0)ǵ(0,1) ǵ (1,0)ǵ(1,1)Ǵ4ঁstateёᇡᒧ3ঁٰ٬ҔǴ‫܌‬аӃόҔ(1,0)ٰ೛ीǶ߄ 2.2൩ࢂ௢ள‫ޑ‬3-bit counterϐstate tableǶௗ๱ճҔԜ߄ӧK-Map΢଺ ᡄᒠ‫ޑ‬ϯᙁ(߄2.3)Ǵள D1 Q2 ‫ ک‬D2 Q2 Q1 Ƕନ3ႝၡ‫ޑ‬ௗጕ൩ࢂ‫ע‬ಃ ΒঁDFF‫ ޑ‬Q2 ᒡрௗဌௗ‫ډ‬ಃ΋ঁDFF‫ޑ‬ᒡΕᆄ D1Ǵӆ‫ ע‬Q2 ‫ ک‬Q1 ᒡΕ 11.

(33) ಃΒക ଯೲନᓎႝၡ. 12. ‫ډ‬2 input‫ޑ‬AND gateࡕ០୏ D2 Ƕ Present State. Next State. Synchronous Input. Q2Q1. Q2Q1. D2D1. 00. 01. 01. 01. 11. 11. 11. 00. 00. ߄2.2 ନ3ႝၡύDFF‫ރޑ‬ᄊᡂඤ D1. Q2. Q1 0. 1. 0. 1. 1. 1. x. 0. Q2. D2. Q2 Q1. Q1 0. 1. 0. 0. 1. 1. x. 0. Q2. ߄2.3 ନ3ႝၡϐK-Map வନ3‫ޑ‬ႝၡाౢғନ2‫ޑ‬ਏ݀Ǵ൩ࢂӃӧႝၡ΢‫ډפ‬΋ঁନ2‫ޑ‬ loopǴӧ‫ځ‬д‫ޑ‬ၡ৩у΢΋ঁOR gate‫ע‬ନΟ‫ૻޑ‬ဦ႖๊௞(კ2.11)Ǵ ନΒନΟႝၡ൩ԜౢғǶკ2.12ࢂ၀ႝၡ‫ޑ‬timing diagramǺmodulus 12.

(34) ಃΒക ଯೲନᓎႝၡ. 13. control (MC)ૻဦࣁhighਔନΒǹMCࣁlowਔନΟǶ. y 2 loop Q1 Q2. MC. CLK. Added logic gate. კ2.11 ନ2ନ3ᡄᒠႝၡკ. MC=1, Ш2. MC=0, Ш3 კ2.12 ନ2ନ3ႝၡϐਔᡂკ ΢ॊ‫ޑ‬ନΒନΟႝၡ٠ߚ୤΋‫ޑ‬ௗ‫ݤ‬ǴЬӢ൩ࢂёаᒧ᏷‫ځ‬дό Ҕ‫(ޑ‬Q1,Q2) stateǶ‫ٯ‬ӵό٬Ҕ(Q1,Q2)=(1,1) stateǴ΋ኬёа೛ीрନ2 ନ3ႝၡ(კ2.13)ǴࣗԿԜௗ‫ݤ‬ᗋё࣪ѐ΋ঁor gate‫ޑ‬٬Ҕ(࣬ၨ‫ܭ‬კ 2.11)Ǵ෧Ͽ᏾ঁႝၡ‫ޑ‬gate delay٬ႝၡೲࡋගϲǶ. 13.

(35) ಃΒക ଯೲନᓎႝၡ. 14. Q2. Q1. Vout. MC. CLK. კ2.13 όӕௗጕ೛ी‫ޑ‬ନ2ନ3ႝၡ. კ2.14 ཥԄନ2ନ3ႝၡϐਔᡂკ dual-modulus‫ঁٿޑ‬ନኧϐёᏹբᓎ౗ό཮΋ኬǴа÷2/3ࣁ‫ٯ‬Ǵ÷2 ёᏹբ‫ޑ‬ᓎࢤ཮К÷3ଯǶӢࣁ÷3К÷2ӭ࿶ၸ΋ঁAND gate delayǴЪ ၀delayሡК΋ঁclk transitionᗋ‫ז‬Ǵ྽clk‫ޑ‬transitionКAND gate delay ᗋ‫ז‬Ǵ൩ό཮Ԗ÷3‫ޑ‬ਏ݀Ƕ!. 2.4.2 Swallow Counterϐ೛ी ԜନᓎᏔࢂҔኧঁdual modulus prescalerբߚӕ‫ޑ؁‬ՍௗǴ೛ी MC‫ޑ‬ౢғਔ໔ٰ‫ׯ‬ᡂ᏾ᡏ‫ޑ‬ନኧǶаკ2.15ࣁ‫ٯ‬Ǵ4ঁ2/3‫ޑ‬prescaler բ ߚӕ ‫؁‬Ս ௗǴന Ͽ‫ ޑ‬ନࢂ ൩ࢂ 24=16Ƕ ӧ MC1 ‫ ޑ‬௓‫ ڋ‬Бय़ Ǵӧ (Q2,Q3,Q4)=(1,1,1)ਔ೛‫ࣁۓ‬3Ǵӧtiming diagram΢൩ё࣮‫ډ‬f2ӧQ2~Q3 ௗᒡр1ਔౢғ3‫୏ޑ‬բǶӕ౛ǴMC2൩೛‫ۓ‬ӧQ3ǵQ4ࣁ1ਔ3Ǵёаӧ timing diagram ΢ ࣮ ‫ ډ‬Ԝ ౜ ຝ Ƕ Ԝ ႝ ၡ ࢎ ᄬ ё ග ‫ ޑ ٮ‬ନ ኧ ࣁ Ǻ N. 16 MC1 2 MC 2 4 MC3 8 MC 4 Ζ. 14.

(36) ಃΒക ଯೲନᓎႝၡ. 15. f in. MC 3. MC 2. MC 1 f2 y2/3. y2/3. f4. MC 4 f8. y2/3. y2/3. f16. f out. კ2.15 ନ16~31ᡄᒠႝၡკ. კ2.16 ନ16~31ႝၡϐਔᡂკ. 2.4.3 ӕ‫؁‬ᚈኳନᓎᏔᆶߚӕ‫ൂ؁‬ኳନᓎᏔ‫่ޑ‬ӝ ӵ݀‫س‬಍ሡा‫׳‬ଯளନኧǴёஒଯೲ‫ޑ‬ᚈኳନᓎᏔᆶߚӕ‫؁‬ନᓎ Ꮤբ่ӝǶ೛ीਔό཮΋ԛஒᚈኳନᓎႝၡ‫ޑ‬ନኧ೛‫ޑۓ‬ϼεǴନኧ ΋εgate delay൩཮ε൯ቚуǴᏹբᓎ౗൩‫ז‬όଆٰǶ೯த཮Ҕନ2ନ3 ‫܈‬ନ4ନ5բଯନኧନᓎႝၡ‫ޑ‬ਡЈǴϐࡕӆҔߚӕ‫ޑ؁‬ନ2ႝၡ‫ע‬ନ ኧቚуǶԜ଺‫ݤ‬ёᗉխനଯᏹբᓎ౗ᡂեǴϐࡕଌ‫ߚډ‬ӕ‫؁‬ନ2ႝၡ ‫ޑ‬ᓎ౗ς࿶ό཮ࡐଯǴёஒନ3ႝၡ‫ޑ‬ႝࢬफ़ե‫ډ‬ёҔጄൎǴ᏾ᡏ‫ޑ‬ ф౗੃઻ёаε൯फ़եǶ კ2.17൩ࢂ΋ঁନ15ନ16‫ٯޑ‬ηǴճҔ΋ঁø405ႝၡу΢‫ঁٿ‬Ս ௗ‫ޑ‬ନ2ႝၡٰჴ౜ǶQ3ǵQ4཮ග‫ٮ‬ѤঁኩᄊǺ(0,0)ǵ(0,1)ǵ(1,0)ǵ(1,1)Ǵ ஒ‫ځ‬ύ‫ޑ‬Οঁኩᄊᆢ࡭ӧନѤǴԶഭΠ‫ޑ‬΋ঁኩᄊ೸ၸᡄᒠ႔ၮᆉ ࡕǴஒନᓎᏔ‫ޑ‬ኳኧ‫ࣁׯ‬ନΟǴ᏾ᡏ‫ޑ‬ନኧ൩ࢂǺ 4 4 4 3 15 Ƕҁ ጄ‫ٯ‬൩ࢂ೛‫(ۓ‬Q3,Q4)=(1,1)ਔǴஒኳኧ‫ࣁۓ‬3(კ2.18)Ƕӵ݀ाள‫ډ‬ନ 16Ǵၟϐ߻ග‫ޑ‬Б‫ݤ‬΋ኬǴӃ‫ډפ‬ନ16‫ૻޑ‬ဦ໺ᒡၡ৩Ǵӆ‫ע‬೷ԋନ 15.

(37) ಃΒക ଯೲନᓎႝၡ. 16. 15‫ޑ‬ၡ৩Ҕ΋ঁOR gate‫ע‬Ѭdisable௞Ƕ ӧ ೛ ी Ԝ ᜪ ႝ ၡ ਔ Ѹ ໪ ੝ ձ ੮ ཀ DFF а Ѧ ‫ ޑ‬ᡄ ᒠ ႔ ౢ ғ ‫ޑ‬ delayǴӵ݀ؒԖ‫୼ى‬ਔ໔ᡣMCౢғ҅ዴ‫ޑ‬logic valueǴନΟ‫ޑ‬ਏ݀൩ ό΋‫ૈۓ‬ჴ౜ǶவԜႝၡ‫ޑ‬timing diagramёа࣮рǴ྽ (Q 3 , Q 4 ) (0,0) ਔ཮Ԗ3ঁclk pulses‫ޑ‬ਔ໔ᡣG2‫ޑ‬ᒡрၲ‫ډ‬ᛙ‫ޑۓ‬logic valueǴ‫܌‬аӧ ଯೲᏹբΠёа෧ᇸG1~G3‫ޑ‬gate delayჹନኧ҅ዴ‫ޑ܄‬ቹៜǶӵ݀೛ ीό‫ؼ‬ǴG2ѝ཮Ԗ΋ঁclk pulse‫ޑ‬ਔ໔ֹԋ҅ዴ‫ޑ‬logic valueǴନኧ‫ޑ‬ ҅ዴ‫܄‬൩ᡂ‫ߚޑ‬தόᛙ‫ۓ‬Ƕ. G3. G2. G1 Q2. Q1. Q3. Q4. f out. Asynchronous y 4. CLK MC. Synchronous y 3 / 4. კ2.17 ନ15ନ16ᡄᒠႝၡკ. ʳ. კ2.18 ନ15ନ16ႝၡϐਔᡂკ 16.

(38) ಃΒക ଯೲନᓎႝၡ. 17. 2.4.4 Multi-Modulus prescalerϐ೛ी ӧ೯ૻ‫س‬಍΢ሡाprescaler‫ޑ‬ନኧૈ୼‫׳‬ӭǴаග‫׳ٮ‬ӭ‫ޑ‬ channelኧᡣ‫س‬಍ᒧҔǶკ2.19‫ޑ‬ନᓎႝၡ൩ࢂදၹၮҔӧsynthesizer ΢‫ޑ‬prescalerࢎᄬǶ‫ځ‬ύх֖΋ঁӕ‫ޑ؁‬ଯೲø4/5ႝၡǴVCO‫ૻޑ‬ဦ җfinᒡΕ‫ډ‬ႝၡύǴf4൩ёள‫ډ‬4‫܈‬5‫ૻޑ‬ဦǶF4࿶ၸ4ঁߚӕ‫ޑ؁‬2ႝ ၡёౢғ24=16‫ޑ‬ନኧǴ‫܌‬аҞ߻ӧfoutςౢғ 16 u 4 64 ‫ޑ‬ନኧǶௗΠ ٰ૸ፕ4/5‫ޑ‬MCౢғ‫ޑ‬БԄǴ྽D0=1ǴMC཮ӧ(Q7,Q6,Q5,Q4)=(1,1,1,0) ਔଌрø5ૻဦ(‫ځ‬ჴΨёаӧ(1,1,1,1)ਔଌрǴѝࢂԜௗ‫ݤ‬ёа෧Ͽ DFF ᒡ р ‫ ޑ‬loading) Ǵ ᏾ ᡏ ନ ኧ ΢ ӭ ନ 1 Ƕ ΋ ኬ ‫ ޑ‬Ǵ ӧ D1=1 ਔ Ъ (Q7,Q6,Q5)=(1,1,0)཮ଌрø5Ƕҗ‫ܭ‬F8Ξ࿶ၸDFF4‫ޑ‬΋ঁclock delayǴ‫܌‬ а཮Ԗ‫ٿ‬ԛ5‫ޑ‬MCౢғǴӧ᏾ᡏନኧ΢ӭନΑ2ঁǶD2‫ک‬D3‫ޑ‬ౢғচ ౛ Ψ ࢂ ࣬ ӕ ‫ ޑ‬Ǵ ന ࡕ ‫ ޑ‬ନ ኧ ൩ ё ၲ ‫ډ‬ N. 64 D0 u 1 D1 u 2 D2 u 4 D3 u 8 Ǵ΋Ӆёග‫ٮ‬64~79ঁନኧǶ. y 4/5. f in. D. Q. D. Q. D. Q. CLK. Q. CLK. Q. CLK. Q. MC Digital Control Ckt N. DFF 4. DFF 5. DFF 6. DFF 7. 64 D0 D1 2 D2 4 D3 8. f out. y 16. კ2.19 ନ64~79ᡄᒠႝၡკ. 17.

(39) ಃΒക ଯೲନᓎႝၡ. 18. კ2.20 ନ64~79ႝၡϐਔᡂკ. 2.4.5 ‫ٿ‬dual-modulusନᓎᏔϐ่ӝ 2.4.3ǵ2.4.4‫ޑ‬ႝၡࢎᄬ೿ࢂҔ΋ঁӕ‫؁‬ଯೲdual-modulusନᓎᏔ ‫ߚک‬ӕ‫ޑ؁‬ø2ႝၡಔԋ‫܌‬ሡ‫ޑ‬ନኧǶӵ݀‫ޔ‬ௗ٬Ҕ‫ঁٿ‬dual-modulus ‫ ޑ‬ନ ᓎ Ꮤ բߚ ӕ‫ ؁‬Ս ௗ Ǵ Ψࢂ ёа ೛ ी р ଯନ ኧЪ ೲ ࡋ ၨ ‫ޑז‬ dual-modulus‫ޑ‬prescalerǶ კ2.25൩ࢂҔ΋ঁ÷2/3‫ک‬΋ঁ÷4/5‫ޑ‬ନᓎᏔբߚӕ‫؁‬ՍௗǴу΢ ΋ঁ÷2‫ک‬΋٤logic gateࡕ൩ёаၲԋ÷22/23Ƕ೭ԛ÷2/3‫ޑ‬ᡄᒠௗጕࢂ όҔ”(Q2,Q1)=00” stateࡕ௢ᄽрٰ‫(ޑ‬კ2.21ǵკ2.22)ǶԶ÷4/5ࢂό Ҕ”(Q3,Q2,Q1)=(0,0,0)ǵ(0,1,0)ǵ(1,0,1)” state(კ2.23ǵკ2.24)Ƕ÷2/3‫ک‬ ÷4/5‫ޑ‬MCࢂҗfout௓‫ڋ‬Ǵ‫܌‬аfoutѝाԖ1ʈ0‫܈‬0ʈ1‫ޑ‬ᡂϯǴѬॺ‫ޑ‬MC ൩ᡂϯ΋ԛǶ÷4/5ႝၡϐࡕᗋௗ΋ঁ÷2ႝၡǴࢂᡣMC‫ޑ‬ᡂϯᓎ౗ࢂ gpvu‫ޑ‬Βϩϐ΋Ǵ‫܌‬а‫׎‬ԋ᏾ᡏ‫ޑ‬ନᓎኧࣁǺ 2 u 4 3 u 5 23 @MC=1ǹ 2 u 5 3u 4. 22 @MC=0Ƕ. კ2.21 ÷2/3ႝၡ(όҔ(0,0)‫ރ‬ᄊ) 18.

(40) ಃΒക ଯೲନᓎႝၡ. 19. კ2.22 ÷2/3ႝၡϐਔᡂკ. კ2.23 ÷4/5ႝၡ. კ2.24 ÷4/5ႝၡϐਔᡂკ. კ2.25 ÷22/23ᡄᒠႝၡკ. კ2.26 ÷22/23ႝၡϐਔᡂკ 19.

(41) ಃΒക ଯೲନᓎႝၡ. 20. 2.5 ჴբ΋Ǵø4/5 Dual-Modulus Prescaler (GaAs HBT) 2.5.1 ࣴ‫୏ز‬ᐒ ᚈኳኧ‫߻ޑ‬࿼ନᓎᏔҞ߻ςቶ‫ޑݱ‬ճҔӧᓎ౗ӝԋᏔύǴԜᅿନ ᓎᏔ‫ڀ‬Ԗ‫ٿ‬ᅿёᒧ᏷‫ޑ‬ନኧǴЪ೏ճҔٰቚуёำԄϯନᓎᏔ‫ޑ‬ନᓎ ጄൎǶࣁΑၮҔӧfractional-N‫ޑ‬Synthesizer΢Ǵ‫ঁٿ‬ନኧ‫ޑ‬ৡѸ໪೛ ‫ࣁۓ‬1ǴջନኧѸ໪ࣁPϷP+1Ƕ. 2.5.2 ࢎᄬᙁϟ Ҟ߻த‫ޑـ‬ᚈኳኧନᓎᏔϐႝၡࢎᄬӵკ2.27‫܌‬ҢǴҗ‫ܭ‬Ԝႝၡ ନΑD-type Flip-FlopϐѦǴѸ໪ќу‫ঁٿ‬NANDᡄᒠ႔Ǵόՠቚуᚐ Ѧ‫ޑ‬ф౗੃઻ǴΨቚуΑ඲Т‫ޑ‬य़ᑈǴ‫׳‬ᝄख़‫ࢂޑ‬फ़եႝၡ‫ޑ‬നଯπ բೲࡋǶࣁΑ‫ׯ‬๓а΢‫ޑ‬લᗺǴҁԛ೛ी‫ޑ‬ᚈኳନᓎᏔஒѦௗ‫ޑ‬ NANDᡄᒠ႔‫ٳ‬ΕD-type flip-flop‫ޑ‬ႝၡύǴӵკ2.28‫܌‬ҢǴόՠёа फ़ե‫ࢬޔ‬ф౗Ǵ‫׳‬ёගϲႝၡ‫ޑ‬ೲࡋǶ. კ2.27 ø4/5ᡄᒠႝၡკ ʳ. 20.

(42) ಃΒക ଯೲନᓎႝၡ. 21. DFF2. DFF1. DFF3. კ2.28 ‫ٳ‬ΕNAND gate‫ޑ‬ø4/5ႝၡ ‫ځ‬ύ᏾ӝϐࡕ‫ޑ‬D-type Flip-Flopႝၡӵკ2.29‫܌‬ҢǴԜDFFࣁӄ ৡ୏ᏹբ‫ޑ‬ႝၡǴёаԖਏ‫ޑ‬फ़եѦࣚᚇૻϷ‫ࢬޔ‬ႝᓸόᛙ‫ޑۓ‬υ ᘋ Ǵ Ъ ࣁ Α ૈ ӧ ଯ ᒡ Ε ᓎ ౗ ਔ ҭ ё ҅ த π բ Ƕ җ ‫ ܭ‬ᒧ Ҕ CML (Current-mode Logic)‫ૻޑ‬ဦӸ‫ڗ‬БԄǴѝ໪ߚதλ‫ޑ‬ႝᓸᡂϯǴջё ղձрᡄᒠǶ Ԝ DFF ӧ ‫ ঁ ؂‬D ࠠ Ӹ ᙹ Ꮤ (d-latch) ϐ ໔ ೿ у ΢ ΋ ಔ Emitter FollowerǴόՠග‫ٮ‬΋ঁଯߔ‫ॄޑל‬ၩǴ‫׳‬ёቚуfan-out‫ޑ‬ኧҞǴЪ җ‫ܭ‬ᡄᒠ٬Ҕ‫ޑ‬ႝࢬό໪ѦࢬǴࡺ‫׳‬ёගଯႝၡ‫ޑ‬πբᓎ౗Ƕ! Vdd. AND Gate D1 D1. Q. D2. Q. D2 CLK CLK Vbias. !. Gnd. კ2.29 ‫ٳ‬ΕNAND gate‫ޑ‬DFF. 21.