[PDF] Top 20 Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
Has 10000 "Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs" found on our website. Below are the top 20 most common "Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs".
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
... Discussion In general, the normal VDD power-on voltage waveform has a rise time on the order of milliseconds and an amplitude of VDD operation ...amplitude in normal ... See full document
5
On-chip transient detection circuit for system-level ESD protection in CMOS ICs
... OUT2 transient responses with ESD voltage of -1500V zapping on the HCP under system-level ESD ...new transient detection circuit for system-level ESD ... See full document
4
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
... new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm ...V CMOS process. The layout area of the new ... See full document
11
Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
... devices with a waffle layout structure had been successfully verified in a ...m CMOS process. As compared with the conventional SSCR devices, the proposed WSCR and WPMSCR have been ... See full document
9
On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation
... Proposed on-chip transient detection circuits realized with (a) NMOS- reset, and (b) PMOS-reset ...functions. With the measurement setup in Fig. 2, the immunity of ... See full document
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Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
... new power-rail ESD clamp circuit is proposed and successfully verified on a 40-nm CMOS process to overcome the leakage current issue while also maintaining very small silicon ... See full document
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High Area-Efficient ESD Clamp Circuit With Equivalent RC-Based Detection Mechanism in a 65-nm CMOS Process
... the ESD clamp device at “ ON ” state under the ESD stress ...the ESD-transient detection circuit suffers not only the larger layout area from the resistance and ... See full document
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Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
... an ESD detection circuit to achieve ultralow standby leakage current and small layout area has been proposed and successfully verified in a 1-V 65-nm fully silicided CMOS ... See full document
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On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
... overview on the design of power-rail ESD clamp circuits in the nanoscale CMOS technology has been ...and circuit techniques used in the ESD-transient ... See full document
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Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
... investigated in a ...higher ESD ro- bustness within a smaller layout area, as compared to the traditional design with the gate-driven NMOS de- ...devices with the parasitic ... See full document
14
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance
... system-level ESD test standard with indirect contact-discharge test ...system-level ESD test consists of a wooden table on the grounded reference plane ...(GRP). In addition, an ... See full document
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System-level ESD protection design with on-chip transient detection circuit
... co-design ESD protection function, a hardware/firmware system co- design combined the transient detection circuit and the power-on reset circuit has been ...normal ... See full document
4
Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
... effective on-chip ESD protection device in CMOS technology due to the highest ESD ...robustness. In this work, the waffle layout structure for SCR can ... See full document
4
Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies
... of ESD protection scheme with LC ...and ESD diode D P ...and ESD diode D N . The ESD diodes D P and D N are used to block the steady leakage current path from V DD to V SS under ... See full document
12
New transient detection circuit for system-level ESD protection
... new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is ...proposed on-chip transient ... See full document
4
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
... pulse with a rise time of 5 ns is applied to the V DD node while the V SS node was grounded to simulate the fast-rising edge of the HBM ESD event, as shown in ...proposed circuit is exactly ... See full document
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A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
... Based upon the understanding of CMOS transient latch-up [lo]-[ 131, the low trigger voltage can be achieved through the proper design of device capaci- tances within [r] ... See full document
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Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
... AIL ESD C LAMP C IRCUIT A. Circuit Schematic The new proposed power-rail ESD clamp circuits of the ultralow standby leakage are shown in ...tively, with p- and n-type ... See full document
9
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
... shown in Fig. 14. The It2 of the input pad under PS-mode ESD stress with silicide blocking on pMOS and nMOS devices is 3 A, and that without silicide blocking is 2 ...silicided in these ... See full document
10
ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology
... TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, ...diode with boron ESD implantation (Dn with ...injecting ESD current through the de- vice, a much larger power is generated at the ... See full document
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