[PDF] Top 20 An efficient VLSI architecture for full-search block matching algorithms
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An efficient VLSI architecture for full-search block matching algorithms
... of search data flow, we use a global distribution of search data connected to each PE row (or ...BMA algorithms can be mapped onto the proposed semi- systolic array or SSA ...processor for N = ... See full document
8
SCALABLE ARRAY ARCHITECTURE DESIGN FOR FULL SEARCH BLOCK MATCHING
... As FSBM is used in different pixel rates, a scalable design that offers variable computing power and accommodates different sizes of search area would avoid the need[r] ... See full document
12
Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms
... cost-effective VLSI architectures for ME ...scalability for different sizes of reference block and search range ...suitable for high-definition video coding ...derived for ... See full document
14
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
... basis for analyzing or evaluating existing ME architectures and makes it easier for new ...FSBM architecture that minimizes bandwidth requirements is ...This architecture is characterized by: ... See full document
12
Low-power parallel tree architecture for full search block-matching motion estimation
... tree architecture is pro- posed for full search block-matching motion ...tree architecture exploits the spatial data correlations between parallel candidate block ... See full document
4
A flexible data-interlacing architecture for full-search block-matching algorithm
... Since different motion-compensation schemes may use different block sizes and require various search area sizes, i t is desirable t o have motion estimation chip flexibl[r] ... See full document
9
An efficient array architecture with data-rings for 3-step hierarchical search block matching algorithm
... second step, the search focuses on the area centered at the winner of the previous step, but the distances between can- didate locations arie shortened by half. In a similar[r] ... See full document
4
A novel scalable architecture with memory interleaving organization for full search block-matching algorithm
... The procedure of a block-matching algorithm is t o find the best matched displaced block from the previous frame Ft-1, within a search range, for each N x N block in th[r] ... See full document
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Low power full-search block-matching motion estimation chip for H.263+
... By the properly design for the PE cell, this architecture can fit variable block size and searching range requirement in a signal chip and still consumes less power. This [r] ... See full document
4
A novel low-power full-search block-matching motion-estimationdesign for H.263+
... VII. C ONCLUSION In this paper, a low-power FSBM motion-estimation architec- ture that supports half-pixel precision, AP mode, PB mode, and RRU mode, was proposed. The complexity of control signals is also considered.The ... See full document
8
Global elimination algorithm and architecture design for fast block matching motion estimation
... its architecture design for fast block matching ...current block, and then to precisely compare the best roughly matched candidate blocks with cur- rent ...fast algorithms, GEA ... See full document
10
Parallel global elimination algorithm and architecture design for fast block matching motion estimation
... and architecture for fast block ...several search positions can be executed in parallel. A parallel GEA architecture design is also in- ...overlapped search area, and resource ... See full document
4
Efficient hierarchical motion estimation algorithm and its VLSI architecture
... Its VLSI Architecture Bing-Fei Wu, Senior Member, IEEE, Hsin-Yuan Peng, Student Member, IEEE, and Tung-Lung Yu Abstract—This paper addresses the development and hardware implementation of an ... See full document
14
A comparison of block-matching algorithms mapped to systolic-array implementation
... four search points located one step size away from the central point along the horizontal and vertical ...additional search points located one step size away from the minimum point are ...new search ... See full document
17
A comparison of block-matching algorithms for VLSI implementation
... This overlapped area data can be stored inside the internal (on-chip) buffer to reduce external memory accesses (bandwidth). Three types of internal buffers are under evaluation: i) type[r] ... See full document
12
Efficient hybrid tree/linear array architectures for block-matching motion estimation algorithms
... Targeting at the joint optimisation of execution latency and input bandwidth, we have shown that by combining the tree technique and the systolic mapping method the propose[r] ... See full document
6
VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER
... 題名: VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER 作者: Li-Chung Chang;Yeong-Kang Lai;Liang-Gee Chen;Jian-Yi La;Tai-Ming Parng 貢獻者: Department of Electrical Engineering National Chung Hsing ... See full document
1
Design of an Efficient VLSI Architecture for 2-D Discrete Wavelet Transforms
... To explore how our proposed architecture works, we use a computation-schedule table to illustrate three levels of separable 2-D DWT computations for an N x N image a[r] ... See full document
6
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
... In fact, the flipping coefficients are not necessarily to be the inverses of the lifting coefficients exactly for releasing the timing accumulation. If the arithmetic operations all belong to two’s complement ... See full document
10
Tree-structure architecture and VLSI implementation for vector quantization algorithms
... 1/0 bandwidth, complicated hardware, and irregular da- t a flow, etc., most of the previous approaches change data sequence to alleviate these problems while sacrific- in[r] ... See full document
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