Organization of This Dissertation

In Chapter 2, a new mixed-voltage I/O buffer realized with only the thin gate-oxide (low-voltage) devices is presented. The new proposed mixed-voltage I/O buffer with simpler

dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25-µm 2.5-V CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications is also presented in this chapter. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers are also compared and discussed. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices can be easily applied in 1×VDD/2×VDD mixed-voltage interface.

In Chapter 3, an input buffer and an output buffer realized with 1-V and 2.5-V low-voltage devices for 3.3-V applications are presented. Due to the high-integration trend of SOC (system-on-a-chip), an electronic system may be integrated into a single chip. Thus, there are digital circuits and analog circuits in a chip. For example, the digital part of a chip is designed with 1-V devices to decrease its power consumption, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. Thus, the traditional I/O circuits are not suitable for this application. An input buffer with the proposed Schmitt trigger circuit in a 0.13-µm 1/2.5-V CMOS process is presented first. Then, an output buffer with the proposed level converter in a 0.13-µm 1/2.5-V CMOS process is also presented in this chapter.

Chapter 4 presents an NMOS-blocking technique for mixed-voltage I/O buffer.

Unlike the traditional mixed-voltage I/O buffer design, the mixed-voltage I/O buffer realized with only 1×VDD devices by using the NMOS-blocking technique can receive 2×VDD, 3×VDD, and even 4×VDD input signal without the gate-oxide reliability issue. In this chapter, the 2×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface.

The 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface.

The proposed NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation of the NMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.

Chapter 5 presents a new charge pump circuit with consideration of gate-oxide reliability issue. Because the charge transfer switches of the new proposed charge pump circuit can be fully turned on and turned off, as well as the output stage doesn’t have the

threshold drop problem, its pumping efficiency can be higher than that of the prior designs.

The gate-drain and the gate-source voltages of all devices in the proposed charge pump circuit don’t exceed VDD, so the proposed charge pump circuit doesn’t suffer the gate-oxide reliability problem. Besides, the proposed charge pump circuit has two pumping branches pumping the output node alternately so the output voltage ripple is small. In this work, two test chips have been implemented in a 0.35-µm 3.3-V CMOS process to verify the proposed charge pump circuit. The measured output voltage of the new proposed 4-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD=3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.

Chapter 6 presents an on-chip ultra-high-voltage charge pump circuit designed with the polysilicon diodes in low-voltage standard CMOS processes. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard (bulk) CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-µm 2.5-V standard CMOS process. The measured output voltage of the 12-stage charge pump circuit with 2.5-V power supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in the 0.25-µm 2.5-V standard CMOS process.

Chapter 7 summarizes the main results of this dissertation. Then, some suggestions for the future works are also addressed in this chapter.

Table 1.1

Key Features of the Semiconductor Scaling Trend (High-Performance Logic Technology) [1]

2005 2006 2007 2008 2009 2010 2011 2012

Gate Length, L (nm) 32 28 25 22 20 18 16 14

Oxide Thickness, tox(Å) 12 11 11 9 7.5 6.5 5 5

Power Supply Voltage, VDD (V)

1.1 1.1 1.1 1 1 1 1 0.9

Threshold Voltage, Vt (mV)

195 168 165 160 159 151 146 148

NMOS Drain Current (μA/μm)

1020 1130 1200 1570 1810 2050 2490 2300

Fig. 1.1. Scaling trends of the oxide thickness and the power supply voltage [1].

Fig. 1.2. A CMOS inverter realized with 2.5-V devices in 5-V environment.

Fig. 1.3. An NMOS load amplifier realized with 2.5-V devices in 5-V environment.

Fig. 1.4. Two CMOS inverters realized with 2.5-V devices in 2.5/5-V mixed-voltage interface.

CHAPTER 2

Mixed-Voltage I/O Buffers With Only Thin Gate-Oxide Devices

In this chapter, the prior designs of mixed-voltage I/O buffers are overviewed first. Then, two new mixed-voltage I/O buffers realized with only thin-oxide devices are presented [26].

The new proposed mixed-voltage I/O buffer 1 with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer 1 has been fabricated and verified in a 0.25-µm CMOS process to serve 2.5/5-V I/O interface.

The subthreshold leakage problem is more serious in the advanced CMOS processes, such as the 0.13-µm CMOS process. Therefore, the new proposed mixed-voltage I/O buffer 2 for high-speed applications is also presented to alleviate this problem. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers (new proposed circuits and prior arts) are also compared and discussed. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices can be easily applied in 1×VDD/2×VDD mixed-voltage interface.

2.1. Issues of Mixed-Voltage I/O Interface

The conventional tri-state I/O buffer with 2.5-V gate-oxide devices in a 0.25-µm CMOS process is shown in Fig. 2.1, where the power supply voltage (VDD) is 2.5 V. However, the input signal at the I/O pad in the mixed-voltage I/O interface may rise up to 5 V in the tri-state input (receive) mode. In the receive mode, the gate voltages of the pull-up PMOS device and the pull-down NMOS device in the I/O buffer are traditionally controlled at 2.5 V and 0 V to turn off the pull-up PMOS device and the pull-down NMOS device by the pre-driver circuit, respectively. When the input signal at the I/O pad rises up to 5 V in the tri-state input mode, the parasitic drain-to-well pn-junction diode in the pull-up PMOS device will be forward biased. Therefore, an undesired leakage current path flows from the I/O pad

to the power supply voltage (VDD) through the parasitic pn-junction diode. Besides, because the gate voltage of the pull-up PMOS device is 2.5 V and the input signal at I/O pad is 5 V, the pull-up PMOS device will be turned on in such tri-state input mode to conduct another undesired leakage current path from the I/O pad to the power supply voltage (VDD). Such undesired leakage currents cause not only more power consumption in the electronic system but also malfunction in the whole electronic system.

Moreover, because the gate-drain voltage (Vgd) of the pull-down NMOS device and the gate-source voltage (Vgs) of the input buffer in Fig. 2.1 with 5-V input signal are larger than their voltage levels in the normal operation, such high voltage across the thin gate oxide of the pull-down NMOS device and the input buffer results in the gate-oxide overstress reliability issue [27]-[29]. In addition, the pull-down NMOS device and the input buffer with a 5-V input signal may suffer serious hot-carrier degradation if their drain-source voltages are too large [13].

Fig. 2.2 shows the mixed-voltage I/O buffer with the dual-oxide (thick-oxide and thin-oxide) devices and an external n-well bias voltage. For such mixed-voltage interface applications, the dual-oxide process provided by foundry is used to avoid the gate-oxide reliability problem [30]-[32]. Since the thick oxide can sustain higher gate voltage, the devices which have the gate-oxide reliability problem can be replaced by the thick-oxide devices to prevent the high-voltage overstress on the thin gate oxide. Therefore, the core circuits in a chip are designed with thin-oxide devices to decrease the chip area and power consumption, but the I/O circuits are designed with thick-oxide devices to avoid the gate-oxide reliability issue. In order to avoid leakage current path from the I/O pad to the power supply (VDD) through the parasitic drain-to-well pn-junction diode in the pull-up PMOS device, the body terminal of the pull-up PMOS must be connected to an extra pad that provides a higher external voltage (VDDH) to bias the body of the pull-up PMOS device. In addition, a gate-tracking circuit is needed to avoid the leakage current path induced by the incorrect conduction of the pull-up PMOS device.

Although the traditional mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias can be used to solve the aforementioned problems, there are still some limitations in this I/O buffer. Using an external bias voltage needs an extra pad to provide another power supply (VDDH), the silicon area and the cost of the whole system are increased. The threshold voltage of the thick-oxide devices is so high that their driving capacities are decreased when their gates are controlled by the pre-driver circuit with low-voltage devices. In addition, because the body terminal of the pull-up PMOS device is

connected to a higher voltage (VDDH), the threshold voltage of the pull-up PMOS device is also increased due to the body effect. Because the driving capacity is decreased, the larger device dimension is required for the pull-up PMOS device to support the desired driving specifications. In turn, it increases the silicon area for such I/O buffer. Therefore, the mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias is unsuitable for the low-cost commercial ICs. Considering these limitations, several mixed-voltage I/O buffers have been reported in [23]-[25], [33], [34], which will be overviewed in this chapter.

2.2. Overview on the Prior Designs of Mixed-Voltage I/O Buffers

2.2.1. Design Concept of Mixed-Voltage I/O Buffers With Thin-Oxide Devices

Fig. 2.3 shows the mixed-voltage I/O buffer realized with thin-oxide devices, a dynamic n-well bias circuit, and a gate-tracking circuit. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. In a 0.25-µm CMOS process, the power supply voltage (VDD) is 2.5 V and the threshold voltage of the devices is about 0.6 V. Because the gate terminal of transistor MN0 is connected to 2.5 V (VDD), the drain voltage of transistor MN1 is about 1.9 V (2.5–0.6=1.9) when the input signal at the I/O pad is 5 V in the tri-state input mode. Hence, the gate-drain voltages and the gate-source voltages of the stacked NMOS devices, MN0 and MN1, are limited below 2.5 V even if the input signal at the I/O pad is 5 V. Therefore, the stacked NMOS devices, MN0 and MN1, can solve the gate-oxide reliability problem.

The gate-tracking circuit shown in Fig. 2.3 is used to prevent the leakage current path due to the incorrect conduction of the pull-up PMOS device when the input signal at the I/O pad is higher than VDD. In the transmit mode, the gate-tracking circuit must transfer the signal from the pre-driver circuit to the gate terminal of the pull-up PMOS device exactly. In the tri-state input mode (receive mode) with 5-V input signal, the gate-tracking circuit will charge the gate terminal of the pull-up PMOS device to 5 V to turn off the pull-up PMOS device completely, and to avoid the leakage current from the I/O pad to the power supply (VDD). On the contrary, the gate-tracking circuit will keep the gate terminal of the pull-up PMOS device at 2.5 V to turn off the pull-up PMOS device completely, and to prevent the overstress on the gate oxide of the pull-up PMOS device, when the input signal at the I/O pad is 0 V in the tri-state input mode.

The dynamic n-well bias circuit shown in Fig. 2.3 is designed to prevent the leakage current path due to the parasitic drain-to-well pn-junction diode in the pull-up PMOS device.

In the transmit mode, the dynamic n-well bias circuit must keep the floating n-well bias at 2.5 V. So, the threshold voltage of the pull-up PMOS device isn’t increased by the body effect. In the tri-state input mode with a 5-V input signal, the dynamic n-well bias circuit will charge the floating n-well to 5 V to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. When the input signal at the I/O pad is 0 V, the dynamic n-well bias circuit will bias the floating n-well at 2.5 V.

Because the floating n-well is clamped to 2.5 V or 5 V through the parasitic diodes by some dynamic n-well bias circuits [24], [33], [34], the voltage on the floating n-well will be a little lower than 2.5 V or 5 V. The lower floating n-well voltage results in the lower threshold voltage of the pull-up PMOS transistor. Thus, the subthreshold leakage current becomes large when the pull-up PMOS transistor is in off state. If the given process has serious subthreshold leakage issue, such as the 0.13-μm or below processes, the dynamic n-well bias circuit must clamp the floating n-well directly to the desired voltage level by the MOS transistor to decrease the subthreshold leakage.

As shown in Fig. 2.3, the extra transistors, MN2 and MP1, are added in the input buffer.

Transistor MN2 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV. Because the gate terminal of transistor MN2 is connected to the power supply voltage (VDD), the input terminal of inverter INV will rise up to 1.9 V (2.5–0.6=1.9) when the input signal at the I/O pad is 5 V in the tri-state input mode. Then, transistor MP1 is used to pull up the input node of inverter INV to 2.5 V when the output node of inverter INV is pulled down to 0 V. Thus, the gate-oxide reliability occurring in the input buffer can be solved.

2.2.2. Prior Designs of Mixed-Voltage I/O Buffers

Fig. 2.4 re-draws the mixed-voltage I/O buffer with stacked pull-up PMOS devices reported in [33]. Signal OE is the output-enable control signal. In the transmit mode, transistor MN1 is turned on and transistor MP2 is turned off, so that this I/O buffer drives the I/O pad according to the output signal Dout. In the tri-state input mode, transistor MN1 is turned off and transistor MP2 is turned on by the control signal OE at logic zero. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP1 and the floating n-well are

pulled up to 5 V through transistor MP2 and the parasitic drain-to-well pn-junction diode in transistor MP0 to prevent the undesired leakage current paths from I/O pad to power supply voltage (VDD), respectively. Although this I/O buffer is simple, transistors MN0, MN1, and MP2 have the gate-oxide reliability problem in the tri-state input mode when the input signal has a 5-V voltage level. Besides, because the stacked PMOS devices with the floating n-well to prevent the leakage current is applied to this I/O buffer, the PMOS devices in stacked configuration occupy more silicon area.

Fig. 2.5 re-draws another mixed-voltage I/O buffer with stacked pull-up PMOS devices and stacked pull-down NMOS devices [34]. This I/O buffer uses transistors MP2, MN3, and MN4 as the gate-tracking circuit and transistors MP0, MP3, and MP4 as the dynamic n-well bias circuit. In the tri-state input mode with the control signal OE at GND, transistor MN4 is turned off and transistor MP2 is turned on. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP3 is biased at 5 V through transistors MP0 and MP2 to avoid the undesired leakage current path due to the incorrect conduction of transistor MP3. The floating n-well is biased at ~5 V through the parasitic drain-to-well pn-junction diode of transistor MP0. In the transmit mode with the OE control signal at VDD, transistor MN4 is turned on so that transistor MP3 is turned on, and transistor MP2 is kept off. Hence, this I/O buffer drives the I/O pad according to the output signal Dout. When the signal at the I/O pad is 0 V, the floating n-well is biased at 2.5 V through transistor MP4. When the input signal at the I/O pad is 2.5 V, the floating n-well is biased at ~2.5 V through the parasitic source-to-well pn-junction diodes of transistors MP3 and MP4. However, transistor MP2 has the gate-oxide reliability problem when the input signal at the I/O pad is 5 V in the tri-state mode. Besides, because the I/O buffer uses two PMOS devices, MP0 and MP3, in stacked configuration to drive the I/O pad, the stacked devices occupy more silicon area.

The mixed-voltage I/O buffer with a depletion PMOS device is re-drawn in Fig. 2.6 [23].

The depletion PMOS device MP2 in the I/O buffer is used as the gate-tracking circuit. In the tri-state mode, if the input signal at I/O pad is 5 V, the gate voltage of transistor MP0 is biased at 5 V through the depletion PMOS device MP2 to avoid the undesired leakage current path through the transistor MP0. This I/O buffer uses an extra pad that is connected to 5-V power supply (VDDH) to avoid the undesired leakage current path through the parasitic drain-to-well pn-junction diode. However, using the depletion device increases mask layer and process modification. Thus, the fabrication cost of such I/O buffer design will be increased. In addition, using the extra n-well bias (VDDH) not only degrades the driving capacity of output device MP0 due to the body effect, but also increases the system cost.

Fig. 2.7 re-draws the mixed-voltage I/O buffer realized with only thin-oxide devices reported in [24]. In Fig. 2.7, the gate-tracking circuit and the dynamic n-well bias circuit are formed by transistors MP1, MP2, MP3, MP4, MN2, MN3, MN4, and MN5. In the transmit mode with signal OE at logic “1”, transistor MN4 is turned on to keep transistors MP3 and MP4 on. Thus, this I/O buffer drives the I/O pad according to signal Dout. Besides, because transistor MP3 is turned on, the floating n-well is biased at 2.5 V by transistor MP3 in the transmit mode. In the tri-state input mode with signal OE at logic “0”, transistor MN4 is kept off. If the input signal at the I/O pad is 5 V, the gate voltages of transistors MP0 and MP4 are

Fig. 2.7 re-draws the mixed-voltage I/O buffer realized with only thin-oxide devices reported in [24]. In Fig. 2.7, the gate-tracking circuit and the dynamic n-well bias circuit are formed by transistors MP1, MP2, MP3, MP4, MN2, MN3, MN4, and MN5. In the transmit mode with signal OE at logic “1”, transistor MN4 is turned on to keep transistors MP3 and MP4 on. Thus, this I/O buffer drives the I/O pad according to signal Dout. Besides, because transistor MP3 is turned on, the floating n-well is biased at 2.5 V by transistor MP3 in the transmit mode. In the tri-state input mode with signal OE at logic “0”, transistor MN4 is kept off. If the input signal at the I/O pad is 5 V, the gate voltages of transistors MP0 and MP4 are