New Charge Pump Circuit Without Gate-Oxide Reliability Issue

The circuit and the corresponding voltage waveforms of the new proposed charge pump circuit with 4 stages are shown in Figs. 3(a) and 3(b), respectively. To avoid the body effect, the bulks of the devices in the proposed charge pump circuit are recommended to be connected to their sources respectively if the given process provides the deep n-well layer.

Clock signals CLK and CLKB are out-of-phase but with the amplitudes of VDD. As shown in Fig. 5.3(a), there are two charge transfer branches, branch A and branch B, in the new proposed charge pump circuit. Branch A is comprised of transistors MN1, MN2, MN3, MN4, MP1, MP2, MP3, and MP4 with the capacitors C1, C2, C3, and C4. Branch B is comprised of transistors MN5, MN6, MN7, MN8, MP5, MP6, MP7, and MP8 with the capacitors C5, C6, C7, and C8. The control signals of branches A and B are intertwined. Besides, clock signals of branches A and B are out-of-phase. When the clock signals of the first and the third pumping stages in the branch A are CLK, those in the branch B are CLKB. Similarly, when the clock signals of the second and the forth pumping stages in the branch A are CLKB, those in the branch B are CLK. Thus, branches A and B can see as two independent charge pump circuits but their output nodes are connected together. Because the clock signals of the branch A and those of the branch B are out-of-phase, the voltage waveforms of nodes 1-4 and those of nodes 5-8 are also out-of-phase. Hence, branches A and B can pump the output voltage to high, alternately. The detailed operations of the new proposed charge pump circuit are described below.

As illustrated in Fig. 5.3(b), the clock signal CLK is low and the clock signal CLKB is high during the time interval T1. At this moment, the voltage difference (V15) between node 1 and node 5 is –VDD. Therefore, transistor MN1 is turned on to transfer the charges from the power supply (VDD) to node 1, but the transistor MN5 is turned off to cut off the path from

node 5 back to the power supply. Similarly, V15 becomes VDD during the time interval T2.

Transistor MN1 is turned off to cut off the leakage path from node 1 back to the power supply, but the transistor MN5 is turned on to transfer the charges from the power supply to node 5.

In the second stage, when the clock signal CLK is low and the clock signal CLKB is high during the time interval T1, V15 and the voltage difference (V26) between node 2 and node 6 are –VDD and VDD, respectively. Therefore, transistors MP5 and MN6 are turned on to transfer the charges from node 5 to node 6, but transistors MP1 and MN2 are turned off to cut off the path from node 2 back to node 1. Similarly, V15 and V26 are VDD and –VDD during the time interval T2, respectively. Transistors MP5 and MN6 are turned off in order to cut off the path from node 6 back to node 5, but transistors MP1 and MN2 are turned on to transfer the charges from node 1 to node 2. The operation of the third pumping stage is similar to that of the second pumping stage.

As shown in Fig. 5.3(a), the output nodes of braches A and B are connected together.

When the clock signal CLK is low and the clock signal CLKB is high during the time interval T1, the voltage difference (V48) between node 4 and node 8 is VDD. Therefore, transistor MP4 is turned on to transfer the charges from node 4 to the output node, but transistor MP8 is turned off to cut off the path from the output node back to node 8. On the other hand, V48

is –VDD during the time interval T2. Hence, the transistor MP4 is turned off and the current path from the output node back to node 4 is cut off. In addition, the transistor MP8 is turned on to transfer the charges from node 8 to the output node.

As shown in Fig. 5.3 (b), the gate-source voltages (Vgs) and gate-drain voltages (Vgd) of all MOSFETs in the new proposed charge pump circuit do not exceed VDD. Thus, there is no high-voltage overstress on the gate oxide of the devices in the new proposed charge pump circuit.

5.3. Verifications and Discussions

5.3.1. Simulation Results and Comparisons

A 0.18-µm 1.8-V CMOS device model is used to verify the design of the new proposed charge pump circuit in HSPICE simulation. Fig. 5.4 shows the simulated voltage waveforms of the new proposed 4-stage charge pump circuit with each pumping capacitor of 1 pF and

5-µA output current. The expected waveforms shown in Fig. 5.3(b) are similar to the simulated waveforms shown in Fig. 5.4. Ideally, the output voltage of the new proposed 4-stage charge pump circuit with 1.8-V power supply voltage (VDD=1.8 V) should be as high as 9 V (1.8×5=9). However, due to the parasitic capacitance at each pumping node and the loading of the output current, the simulated output voltage of the new proposed charge pump circuit is around 8.39 V.

Fig. 5.5 shows the simulated output voltages of the proposed charge pump circuit under different output currents and power supply voltages (VDD). When the output current is increased, the output voltages of the proposed charge pump circuit under different power supply voltages (VDD) are decreased. If the new proposed charge pump circuit only drives the capacitive load, the output voltages of the proposed charge pump circuit under different power supply voltages (VDD) are close to 5×VDD. If the supply voltage is too low and the output current is too high, the proposed charge pump circuit can not pump the output voltage high.

The simulated output voltages of the Dickson charge pump circuit [63], Wu and Chang’s charge pump circuit [75], and the new proposed charge pump circuit with different output currents are compared in Fig. 5.6. Actually, the pumping capacitors of a charge pump circuit take a great part in silicon area. For fair comparison, the total pumping capacitors of these charge pump circuits must be equaled. Therefore, the pumping capacitors in the proposed charge pump circuit, in Wu and Chang’s charge pump circuit, and in the Dickson charge pump circuit are set to 1 pF, 1.6 pF (1×8/5=1.6), and 2 pF (1×8/4=2), respectively. As shown in Fig. 5.6, the output voltages of the proposed charge pump circuit with different output currents are much higher than those of other charge pump circuits. Especially, with the higher output current of 30 μA, the proposed charge pump circuit still has the better pumping performance than others. Since the proposed charge pump circuit has two pumping branches pushing the charges to the output node alternately, the degradation of the output voltage is smaller while the output current increases. Besides, the MOSFET switches in the new proposed charge pump circuit are fully turned on to transfer the charges, but all MOSFET switches in the Dickson charge pump circuit and the output stage of Wu and Chang’s charge pump circuit are diode-connected transistors, which have the threshold voltage drop problem.

Therefore, the proposed charge pump circuit has better pumping performance than others, as shown in Fig. 5.6.

Fig. 5.7 compares the simulated output voltages of the Dickson, Wu and Chang’s, and the new proposed charge pump circuits under different power supply voltages (VDD) without

output current loading. As shown in Fig. 5.7, the output voltages of these three charge pump circuits are degraded when the power supply voltage is decreased. However, the new proposed charge pump circuit still has higher output voltages under the lower power supply voltage because the proposed charge pump circuit has better pumping efficiency. Thus, the proposed charge pump circuit is more suitable in low-voltage processes than the prior designs.

Branches A and B in the new proposed charge pump circuit can pump the output voltage alternately, but Wu and Chang’s charge pump circuit and the Dickson charge pump circuit only pump the charges to the output node per clock cycle. The simulated output waveforms of these charge pump circuits with 20-µA output current are shown in Fig. 5.8, where ΔV is the amplitude of the output voltage ripple. As shown in Fig. 5.8, the output voltage ripple of the proposed charge pump circuit (0.166%) is much smaller than those of Wu and Chang’s charge pump circuit (0.457%) and the Dickson charge pump circuit (0.762%). Therefore, the output voltage of the new proposed charge pump circuit is more stable than those of the other charge pump circuits. If the output voltage ripple is still large, a low-pass filter should be connected to the output node of the charge pump circuit to filter the voltage ripple [78] or a feedback loop can be applied in the charge pump circuit to stabilize the output voltage [91], [92].

5.3.2. Silicon Verifications

In this work, two test chips have been fabricated in a 0.35-µm 3.3-V CMOS process to verify the proposed charge pump circuit. Fig. 5.9 shows the simulated output voltages of proposed charge pump with each pumping capacitor of 2 pF, the Dickson charge pump circuit with each pumping capacitor of 4 pF, and Wu and Chang’s charge pump circuit with each pumping capacitor of 3.2 pF in the 0.35-μm 3.3-V CMOS process. As shown in Fig. 5.9, the proposed charge pump circuit has better pumping performance. The photographs of these two test chips are shown in Figs. 10(a) and 10(b), respectively. These two test chips include the proposed 4-stage charge pump circuit with each pumping capacitors of 2 pF, the proposed 2-stage charge pump circuit with each pumping capacitor of 2 pF, Wu and Chang’s 4-stage charge pump circuit with each pumping capacitor of 2 pF, Wu and Chang’s 4-stage charge pump circuit with each pumping capacitor of 3.2 pF, the Dickson 4-stage charge pump circuit with each pumping capacitor of 2 pF, the Dickson 4-stage charge pump circuit with each

pumping capacitor of 4 pF, the proposed 4-stage charge pump circuit with each pumping capacitor of 4 pF, and the proposed 3-stage charge pump circuit with each pumping capacitor of 2 pF. To drive capacitive load, the measured output voltage of the new proposed 4-stage charge pump circuit with each pumping capacitor of 2 pF is around 8.8 V under 3.3-V power supply voltage (VDD=3.3 V). Fig. 5.11 shows the measured output voltages of the 4-stage charge pump circuits with different output currents. The measured results in Fig. 5.11 is little lower than the simulated results in Fig. 5.9 because of the parasitic resistance and capacitance from the test chips, the bonding wires, and the packages. The parasitic resistance and capacitance may results in the overlapping clock signals, which will lower the pumping efficiency. However, similar to the simulation results, the proposed charge pump circuit has better pumping performance than others, as shown in Fig. 5.11. Besides, the output voltage (~9 V) of the proposed charge pump circuit is limited by the breakdown voltage of the parasitic drain-to-bulk pn-junction diode under the low output current. If the output voltage of the charge pump circuit is larger than the breakdown voltage of the pn-junction diode, the charges leak through this diode and the output voltage of the charge pump circuit is kept at the breakdown voltage. Fig. 5.12 compares the measured output voltages of the proposed 2-stage, 3-stage, and 4-stage charge pump circuits with each pumping capacitor of 2 pF under 2-V power supply (VDD=2 V), respectively. Similarly, the measured output voltage of the proposed 4-stage charge pump circuit in Fig. 5.12 is also limited by the breakdown voltage of the parasitic pn-junction diode at low output current.

5.3.3. Discussions

Gate-oxide reliability is a time-dependent issue [8], [57]. The time period during the voltage overstress on the gate oxide is accumulated to induce the oxide breakdown. Hence, the DC stress is more harmful to the gate oxide than the short AC stress (transient stress). The diode-connected MOSFET in the Dickson charge pump circuit is used to transfer charges from the present stage to the next stage. When the diode-connected MOSFET is turned off to prevent the charges flowing back to the previous stage, the voltage across the gate oxide of the diode-connected MOSFET is around 2×VDD–Vt, where Vt is the threshold voltage of the diode-connected MOSFET. The diode-connected MOSFET will suffer serious gate-oxide overstress, so the gate oxide of the diode-connected MOSFET may be damaged after operation. In Wu and Chang’s charge pump circuit, not only these diode-connected

MOSFETs but also the charge transfer switches (CTSs) and their control circuits will suffer serious high-voltage overstress on the gate oxide. In the proposed charge pump circuit, the gate-oxide reliability issue has been considered. The gate-source voltages (Vgs) and gate-drain voltages (Vgd) of devices in the proposed charge pump circuit don’t exceed VDD whenever it is in the normal operation, start-up, or turn-off states. Therefore, the proposed charge pump circuit is better for applications in low-voltage CMOS processes.

As shown in Figs. 5.11 and 5.12, the output voltage of the proposed charge pump circuit will be limited by the breakdown voltages of the parasitic pn-junctions. As the CMOS process is scaled down, the breakdown voltages of the parasitic pn-junctions become lower.

Thus, the output voltage limitation of the charge pump circuit will become more serious. In [79], the charge pump circuit is designed in the SOI (silicon-on-insulator) process without the limitation of the breakdown voltages of the pn-junctions. However, the SOI process is more expensive than the bulk CMOS process. The charge pump circuit consisting of the polysilicon diodes, which is fully compatible to the standard bulk CMOS process, may be a good candidate to implement the charge pump circuit without the limitation of the breakdown voltages of the parasitic pn-junctions in the future [80]. The charge pump circuit designed with the polysilicon diodes will be presented in Chapter 6.

5.4. Summary

A new charge pump circuit realized with only low-voltage devices without suffering the gate-oxide reliability issue has been presented. Because the charge transfer switches of the new proposed charge pump circuit can be fully turned on and turned off, as well as the output stage doesn’t have the threshold drop problem, its pumping efficiency is higher than that of the prior designs. The gate-drain and the gate-source voltages of all devices in the proposed charge pump circuit don’t exceed VDD, so the proposed charge pump circuit doesn’t suffer the gate-oxide reliability problem. Two test chips have been implemented in a 0.35-µm 3.3-V CMOS process. The experimental results have shown that the new proposed 4-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive load is around 8.8 V under 3.3-V power supply (VDD=3.3 V). With the higher pumping gain and no overstress across the gate oxide, the new proposed charge pump circuit is more suitable for applications in low-voltage CMOS integrated circuits to generate the specified high voltage.

(a)

(b)

Fig. 5.1. 4-stage (a) diode, and (b) Dickson, charge pump circuits.

(a)

(b)

Fig. 5.2. (a) Circuit, and (b) Corresponding voltage waveforms, of the 4-stage Wu and Chang’s charge pump circuit.

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(b)

Fig. 5.3. (a) Circuit, and (b) Corresponding waveforms, of the new proposed charge pump circuit with 4 pumping stages.

Fig. 5.4. Simulated waveforms on CLK, CLKB, nodes 1-8, and Vout in the new proposed 4-stage charge pump circuit.

Fig. 5.5. Simulated output voltages of the new proposed 4-stage charge pump circuit under different output currents and power supply voltages (VDD).

Fig. 5.6. Simulated output voltages of the Dickson, Wu and Chang’s, and the proposed charge pump circuits with 4 stages under different output currents with 1.8-V power supply (VDD=1.8 V).

Fig. 5.7. Simulated output voltages of the Dickson, Wu and Chang’s, and the proposed charge pump circuits with 4 stages under different VDD without output current loading.

Fig. 5.8. Simulated output waveforms of the Dickson, Wu and Chang’s, and the proposed charge pump circuits of 4 stages with 20-µA output current and 1.8-V power supply (VDD=1.8 V).

Fig. 5.9. Simulated output voltages of different 4-stage charge pump circuits in the 0.35-µm 3.3-V CMOS process under different output currents with the power supply voltage (VDD) of 3.3 V.

(a)

(b)

Fig. 5.10. Photographes of charge pump circuits in (a) chip 1, and (b) chip 2, fabricated in the 0.35-µm 3.3-V CMOS process.

Fig. 5.11. Measured output voltages of different charge pump circuits with 3.3-V power supply (VDD=3.3 V), where the stage number is 4.

Fig. 5.12. Measured output voltages of the new proposed 2-stage, 3-stage, and 4-stage charge pump circuits with 2-V power supply (VDD=2 V) under different output currents.

CHAPTER 6

Ultra-High-Voltage Charge Pump Circuit With Polysilicon Diodes in Low-Voltage Standard CMOS Processes

This chapter presents an on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage standard CMOS processes. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-µm 2.5-V standard CMOS process. The output voltage of the 4-stage charge pump circuit with 2.5-V power supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-µm 2.5-V bulk CMOS process.

6.1. Background

Charge pump circuits can generate the dc voltages those are higher than the normal power supply voltage (VDD) or lower than the ground voltage (GND). Charge pump circuits are usually applied to the nonvolatile memories, such as EEPROM and flash memories, to write or to erase the floating-gate devices [59]. Besides, charge pump circuits can be also used in some low-voltage designs to improve the circuit performance [81]. In the MEMS (micro electro mechanical systems) and electroluminescent display applications, the charge pump circuit must provide the output voltage higher than 15 V, even up to 60 V [79], [82]-[84]. Early, the pn-junction diodes were applied in the charge pump circuit. However, it is difficult to implement the fully independent pn-junction diodes in the common silicon substrate. The charge pump circuit realized with transistors in the diode-connected style was reported by Dickson [63]. Owing to the body effect, the pump efficiency of the Dickson charge pump circuit is degraded as the number of the stages increases. Several modified

charge pump circuits based on the Dickson charge pump circuit were reported to enhance the pumping efficiency [75], [77].

As the semiconductor process is scaled down, the normal circuit operation voltage (VDD) of the integrated circuits (ICs) is also decreased. The reliability issue must be considered to design the charge pump circuit in the deep-sub-micron CMOS processes, such as the gate-oxide overstress problem [77]. Fig. 6.1(a) shows the cross section of the p+/n-well diode in the grounded p-substrate with the shallow-trench isolation (STI). The p+/n-well diode is one kind of the pn-junction diodes in the bulk CMOS process. In Fig. 6.1(a), an undesired parasitic pn-junction exists between the n-well and the grounded p-type substrate.

If the voltage on the cathode of the p+/n-well diode is larger than the junction breakdown voltage between the n-well and the grounded p-substrate, the charges on the cathode will leak to ground through the parasitic pn-junction. Fig. 6.1(b) shows the cross section of the diode-connected NMOS, whose gate and drain are connected together, in the grounded p-substrate. In Fig. 6.1(b), an undesired pn-junction parasitizes between the n+ region (source/drain) and the grounded p-type substrate. Similarly, if the voltages on the cathode or

If the voltage on the cathode of the p+/n-well diode is larger than the junction breakdown voltage between the n-well and the grounded p-substrate, the charges on the cathode will leak to ground through the parasitic pn-junction. Fig. 6.1(b) shows the cross section of the diode-connected NMOS, whose gate and drain are connected together, in the grounded p-substrate. In Fig. 6.1(b), an undesired pn-junction parasitizes between the n+ region (source/drain) and the grounded p-type substrate. Similarly, if the voltages on the cathode or