Summary

Two new mixed-voltage I/O buffers with the stacked NMOS technique, dynamic n-well technique, and gate-tracking circuit have been presented in this chapter. The new proposed mixed-voltage I/O buffer 1 has been implemented in a 0.25-µm 2.5-V CMOS process, which can be operated in the 2.5/5-V signal environment without the gate-oxide reliability problem.

The new proposed mixed-voltage I/O buffer 2 can be applied for high-speed applications without the gate-oxide reliability problem and the circuit leakage issue. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices can be easily applied in 1×VDD/2×VDD mixed-voltage interface.

TABLE2.1

Mixed-voltage

TABLE 2.4

Fig. 2.1. Conventional tri-state I/O buffer in a 0.25-µm CMOS process that will suffer the circuit leakage and gate-oxide reliability issue in the mixed-voltage I/O interface.

Fig. 2.2. Mixed-voltage I/O buffer with dual-oxide option and an external n-well bias.

Fig. 2.3. Basic design concept for mixed-voltage I/O buffer realized with only thin-oxide devices.

Fig. 2.4. Mixed-voltage I/O buffer with stacked pull-up PMOS devices [33].

Fig. 2.5. Mixed-voltage I/O buffer with stacked pull-up PMOS devices and stacked pull-down NMOS devices [34].

Fig. 2.6. Mixed-voltage I/O buffer with a depletion PMOS device MP2 [23].

Fig. 2.7. Mixed-voltage I/O buffer realized with only thin-oxide devices [24].

Fig. 2.8. Mixed-voltage I/O buffer realized with only thin-oxide devices [25].

Fig. 2.9. New mixed-voltage I/O buffer 1 with only thin-oxide devices.

(a)

(b)

Fig. 2.10. Simulated waveforms of the new proposed mixed-voltage I/O buffer 1 with a 20-pF load and 50-MHz I/O signal in (a) the transmit mode, and (b) the tri-state (receive) mode.

Fig. 2.11. Die photograph of the new proposed mixed-voltage I/O buffer 1 fabricated in a 0.25-µm 2.5-V CMOS process.

(a)

(b)

(c)

Fig. 2.12. Measured waveforms of the new proposed mixed-voltage I/O buffer 1 with 1-MHz I/O signal in (a) the transmit mode, (b) the tri-state input mode with 2.5-V input, and (c) the tri-state input mode with 5-V input.

Fig. 2.13. New proposed mixed-voltage I/O buffer 2 with only thin-oxide devices.

(a)

(b)

Fig. 2.14. Simulated waveforms of the new proposed mixed-voltage I/O buffer 2 with a 20-pF load and 50-MHz I/O signal in (a) the transmit mode, and (b) the tri-state input (receive) mode.

(a)

(b)

Fig. 2.15. Simulated waveforms to compare the voltage levels of the floating n-well in the new mixed-voltage I/O buffers 1 and 2, during the signal transition on the I/O pad. (a) In transmit mode, and (b) in receive mode.

CHAPTER 3

3.3-V Input Buffer and Output Buffer in 0.13-µm 1/2.5-V CMOS Process

With 3.3-V interface, such as PCI-X application, the high-voltage overstress on the gate oxide is a serious reliability problem to design the I/O circuits by only using 1/2.5-V low-voltage devices in a 0.13-µm CMOS process. Thus, an input buffer [37] and an output buffer [38] realized with 1/2.5-V low-voltage devices for 3.3-V applications are presented in this chapter, respectively. Besides, a new Schmitt trigger circuit [37] and a new level converter [38] are also presented in this chapter.

3.1. Input Buffer

3.1.1. Background

As the semiconductor process is scaled down, the thickness of gate oxide becomes thinner in order to decrease the core power supply voltage (VDD) [1]. However, the board voltage (VCC) is still kept as high as 3.3 V (or 5 V), such as PCI-X interface [39]. There are three problems on a MOSFET when the operating voltage is higher than its normal voltage.

Higher drain-to-source voltage (Vds) may cause the serious hot-carrier effect which results in the long-term lifetime issue [6]. The drain-to-bulk pn-junction breakdown may occur if the operating voltage is too high. The high-voltage stress across the thinner gate oxide could also destruct the gate oxide [27]. Thus, the I/O circuit must be designed carefully to overcome these problems, especially the high-voltage gate-oxide stress [23]-[29].

Schmitt trigger circuit has been widely used in the input buffers to increase noise immunity. The conventional input buffer, which consists of a Schmitt trigger and a level-down converter, is shown in Fig. 3.1. The Schmitt trigger circuit receives input signals from the I/O pad and rejects input noise. Then, the level-down converter can convert the signal swing from VCC to VDD, where VCC is the board voltage and VDD is the core power

supply voltage. The circuit and the transfer curve of the conventional Schmitt trigger circuit [40], [41] are shown in Figs. 3.2(a) and 3.2(b), respectively. Transistors P1, P2, P3, N1, N2, and N3 in Fig. 3.2(a) are the I/O devices with the normal operation voltage of VDD. If the board voltage (VCC) is equal to VDD, the gate-drain and gate-source voltages of transistors P1, P2, P3, N1, N2, and N3 in Fig. 3.2(a) will not exceed VDD. Thus, the conventional Schmitt trigger circuit can be operated safely without suffering high-voltage gate-oxide overstress. As shown in Fig. 3.2(b), the conventional Schmitt trigger circuit with different high-to-low and low-to-high transition threshold voltages (VH and VL) has better noise immunity than the inverter. When the input signal IN goes up to VCC from GND, the threshold voltage of the conventional Schmitt trigger circuit is VH. In other words, the output signal OUT is pulled low when the signal IN exceeds the high-to-low threshold voltage (VH).

Similarly, when the input signal IN goes down to GND from VCC, the threshold voltage of the conventional Schmitt trigger circuit is VL. In other words, the output signal OUT is pulled up when the input signal IN is lower than the low-to-high threshold voltage (VL). Hence, the noise immunity of the conventional Schmitt trigger circuit is better than that of inverter. The threshold voltages VH and VL can be adjusted by controlling the device dimensions of those transistors [35].

Several modified Schmitt trigger circuits were reported for different applications [42]-[45]. Fig. 3.3(a) shows the Schmitt trigger circuit reported in [42]. The extra bias voltage VB and the extra transistors P4 and N4 are used to adjust the two threshold voltages VL and VH. In [43], a multi-layer Schmitt trigger circuit was reported to increase the voltage difference between the two threshold voltages VH andVL. The two-layer Schmitt trigger circuit is shown in Fig. 3.3(b). However, as the power supply voltage is scaled down, the multi-layer Schmitt trigger circuit can not be operated correctly. In [44], a low-power Schmitt trigger circuit was reported. An alternative circuit, which has the hysteresis characteristic similar to that of a conventional Schmitt trigger, was reported in [45].

However, the aforementioned Schmitt trigger circuits have high-voltage gate-oxide overstress problem if the board voltage (VCC) is higher than VDD. For example, the digital part of a chip is designed with 1-V devices to decrease its power dissipation, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. The gate-source voltages and the gate-drain voltages of transistors P1, P2, P3, N1, N2, and N3 in Fig. 3.2(a) will be higher than 2.5 V if the board voltage (VCC) is 3.3 V and the I/O devices are 2.5-V devices. Thus, all transistors in Fig. 3.2(a) will suffer the high-voltage gate-oxide overstress problem.

Furthermore, the other Schmitt triggers [42]-[45] also suffer the gate-oxide reliability problem in such a mixed-voltage interface. Thus, a new Schmitt trigger circuit for the input buffer is presented in this section. Then, the whole input buffer realized with the 1/2.5-V devices to receive 3.3-V input signals is presented.

3.1.2. Schmitt Trigger Design

The new proposed Schmitt trigger circuit is shown in Fig. 3.4. All devices of the proposed Schmitt trigger circuit in Fig. 3.4 are the I/O devices with the normal operating voltage of 2.5 V. In a 0.13-µm 1/2.5-V CMOS process, the I/O devices is realized with 2.5-V gate oxide and the core circuits are operated with 1-V power supply. Therefore, the voltage across the gate oxide of the I/O devices in this process can not exceed 2.5 V. As shown in Fig.

3.4, because the drains of transistors P3 and N3 are connected to 1 V (VDD), the gate-drain voltages of transistors P3 and N3 will not exceed 2.5 V. The maximum gate-drain and gate-source voltages of transistors P3 and N3 are around 2.3 V (3.3−1=2.3). Because the gates of transistors P2 and N2 are connected to 1 V (VDD), the gate-drain voltages and gate-source voltages of transistors P2 and N2 will not exceed 2.5 V. The maximum gate-drain voltages of transistors P2 and N2 are also around 2.3 V (3.3−1=2.3). If the gate voltage of transistor P1 (node A) is kept higher than 0.8 V (3.3−2.5=0.8) and the gate voltage of transistor N1 (node B) is kept lower than 2.5 V, transistors P1 and N1 don’t have the high-voltage gate-oxide overstress problem. Hence, in order to prevent the gate voltage of transistor P1 under 0.8 V, transistors P4, P5, P6, and P7 are added. Similarly, transistors N4, N5, N6, and N7 are designed to prevent the gate voltage of transistor N1 over 2.5 V.

When the input signal (IN) stays at 3.3 V (VCC), the voltage on node A is also kept at 3.3 V because transistor P6 is turned on. When the input signal (IN) goes to 0 V, the voltage on node A is kept at 2·|Vtp| because transistors P4 and P5 are in diode-connected structure. In the 0.13-µm 1/2.5-V CMOS process, |Vtp| of 2.5-V device is about 0.6 V. Therefore, the minimum gate voltage of transistor P1 (node A) is about 1.2 V. However, the diode-connected transistors P5 and P6 may make the voltage on node A to 0 V when the input signal (IN) stays at 0 V for a long time, because of the subthreshold current of transistors P5 and P6. An extra transistor P7 is added to avoid the voltage on node A under 1 V caused by the subthreshold current of transistors P5 and P6. Hence, as the voltage on node A is under 1 V, transistor P7 will be turned on to keep the voltage at 1 V.

When the input signal (IN) stays at 0 V, the voltage on node B is kept at 0 V because transistor N6 is turned on. When the input signal (IN) goes to 3.3 V, the voltage on node B is kept at 3.3−2·|Vtn|, because transistors N4 and N5 are in diode-connected structure. In the 0.13-µm 1/2.5-V CMOS process, |Vtn| of 2.5-V device is about 0.5 V. Therefore, the maximum gate voltage of transistor N1 (node B) is about 2.3 V. However, the diode-connected transistors N5 and N6 may make the voltage on node B to 3.3 V, when the input signal (IN) stays at 3.3 V for a long time, due to the subthreshold current of transistors N5 and N6. Hence, a weak transistor (long-channel transistor) N7 is added to avoid the voltage on node B over 2.5 V caused by the subthreshold current of transistors N5 and N6. If node B goes to 3.3 V, transistor N7 provides a small current to keep the gate voltage of transistor N1 under 2.5 V.

In addition, transistor N6 in Fig. 3.4 can be a 2.5-V native-Vt transistor instead of a 2.5-V normal-Vt transistor. The threshold voltage of the native-Vt transistor is close to 0 V, which is lower than that of the normal-Vt transistor [46], [47]. In the 0.13-µm 1/2.5-V CMOS process, the threshold voltage of the 2.5-V native-Vt transistor is about 0.03 V. Because the gate-source voltage of transistor N6 is small, the voltage on node B follows input signal IN to 0 V slowly. Thus, a native-Vt transistor is more suitable than a normal-Vt transistor to implement the transistor N6 for high-speed applications. Because the native-Vt device has been one of the standard devices in a 0.13-µm 1/2.5-V CMOS process, no extra process or mask is needed [47]. Fig. 3.5 compares the voltage waveforms at node B when transistor N6 is a native-Vt transistor or a normal-Vt transistor in the 0.13-µm 1/2.5-V CMOS process. As shown in Fig. 3.5, the voltage on node B is pulled down more quickly when transistor N6 is implemented by a native-Vt transistor.

A 0.13-µm 1/2.5-V CMOS SPICE model is used to simulate the new proposed Schmitt trigger circuit. The simulated waveforms at the nodes IN, OUT, A, and B of the new proposed Schmitt trigger circuit are shown in Fig. 3.6. The input signal can be correctly translated to the output by the proposed Schmitt trigger circuit. Besides, the voltage level at node A is indeed kept higher than 0.8 V, and that of node B is kept lower than 2.5 V. Therefore, transistors P1 and N1 of the proposed Schmitt trigger circuit don’t suffer high-voltage gate-oxide reliability issue in a 3.3-V environment. Besides, the Vgs and Vgd of all devices are not over 2.5 V. The Vds of all devices are also not over 2.5 V when the input signal is high or low. Hence, the new proposed Schmitt trigger circuit can receive the high-voltage input signals without suffering gate-oxide reliability and hot-carrier degradation issues, whereas it is realized by only using the low-voltage devices with thin gate oxide.

The simulated transfer curve of the new proposed Schmitt trigger circuit is shown in Fig.

3.7. The new proposed Schmitt trigger circuit has an obvious hysteresis characteristic. In Fig.

3.7, the transition threshold voltages VL and VH of the new proposed Schmitt trigger circuit are around 1.1 V and 2.6 V, respectively.

3.1.3. Whole Input Buffer Design

Fig. 3.8 shows the whole input buffer design with the proposed Schmitt trigger circuit and the level-down converter. The proposed Schmitt trigger circuit receives the input signals from the I/O pad and rejects input noise. Then, the level-down converter can convert the signal swing from VCC (3.3 V) to VDD (1 V). In the level-down converter, transistor N2 is a 2.5-V (thick-oxide) device and transistors P1, P2, and N1 are 1-V (thin-oxide) devices. As the input voltage of the level-down converter is GND, the voltage on node A is also at GND due to transistor N2 and the voltage on node OUT is at VDD. As the input voltage of the level-down converter is VCC, the voltage on node A is limited at VDD−Vt due to transistor N2, whose gate is bias at VDD. Because the voltage on node A is at VDD−Vt, the voltage on node OUT is pulled down to ground and then transistor P2 is turned on. Finally, the voltage on node A is at VDD. Thus, the level-down converter can convert the signal swing from VCC to VDD.

3.1.4. Experimental Results

The new proposed Schmitt trigger circuit and the whole input buffer have been fabricated in a 0.13-µm 1/2.5-V 1P8M CMOS process with Cu interconnects. The layout of the new proposed Schmitt trigger circuit is shown in Fig. 3.9. Because the proposed Schmitt trigger circuit is connected to an input pad, some guard rings surrounding the whole Schmitt trigger circuit are used to prevent the latch-up problem [36]. The layout area of the new proposed Schmitt trigger circuit including the guard rings is only 8.7 µm × 19 µm.

The measured waveforms at the input node and the output node of the new proposed Schmitt trigger circuit are shown in Fig. 3.10. The new proposed Schmitt trigger can operate correctly with 0-to-3.3-V input signals. In Fig. 3.11, the input signal is applied with a slow triangular waveform. Therefore, the transition threshold voltages VL and VH of the new proposed Schmitt trigger circuit can be measured at the crossing points between the input

signal and output signal. The measured DC transfer curve of the new proposed Schmitt trigger circuit is shown in Fig. 3.12. These two transition threshold voltages VL and VH of the fabricated Schmitt trigger circuit are around 1 V and 2.5 V, respectively. Due to the process variation, the measured transition threshold voltages are slightly different from the simulated transition threshold voltages.

The measured waveforms at the nodes IN and OUT of the whole input buffer are shown in Fig. 3.13 with a 133-MHz 3.3-V input signal. The 3.3-V input signal is received by the proposed Schmitt trigger circuit, and then the signal swing is converted from 3.3 V to 1 V by the level-down converter. As shown in Fig. 3.13, the input buffer can be successfully operated in the 133-MHz 3.3-V environment.

3.1.5. Summary

A new Schmitt trigger circuit realized with only low-voltage devices to receive the high-voltage signals is proposed. The new Schmitt trigger circuit has been fabricated in a 0.13-µm 1/2.5-V 1P8M CMOS process. The proposed Schmitt trigger circuit, which consists of low-voltage (2.5-V) devices, can be operated correctly without suffering high-voltage gate-oxide overstress in a 3.3-V interface environment. The measured results have shown that the two transition threshold voltages VL and VH of the new proposed Schmitt trigger are 1 V and 2.5 V, respectively. The whole input buffer, which is consisted with the proposed Schmitt trigger and a level-down converter, has been verified to be successfully operated in the 133-MHz 3.3-V environment.

3.2. Output Buffer

3.2.1. Background

The thickness of gate oxide becomes thinner in order to decrease the core power supply voltage (VDD) as the semiconductor technology is scaled down [1]. This results in lower power consumption. However, the board voltage (VCC) is still kept as high as 3.3 V (or 5 V), such as PCI-X interface [39]. There are three problems on a MOSFET when the operating voltage is higher than its normal voltage. Higher drain-to-source voltage (Vds) may cause the serious hot-carrier effect which results in the long-term lifetime issue [6]. The drain-to-bulk

pn-junction breakdown may occur if the operating voltage is too high. The high-voltage overstress across the thinner gate oxide could also destruct the gate oxide [27], [28].

Therefore, the I/O circuits must be designed carefully to overcome these problems, especially the high-voltage gate-oxide overstress [23]-[26].

Recently, the dual-oxide (thin-oxide and thick-oxide) processes have been supported by some manufacturing companies [32], [47], [48]. For example, the thin-oxide devices are 1-V or 1.2-V devices and the thick-oxide devices are 1.8-V, 2.5-V, or 3.3-V devices in a 0.13-µm CMOS process [47], [48]. The thin-oxide devices are used to design the digital circuits to decrease silicon area and power consumption. The thick-oxide devices are used to design the analog circuits to improve circuit performance or the I/O circuits to avoid the gate-oxide reliability issue. Fig. 3.14 shows the conventional tri-state I/O buffer co-designed with thin- and thick-oxide devices. As shown in Fig. 3.14, transistors P1 and N1 are the thick-oxide devices, which can sustain the voltage level of VCC to avoid the gate-oxide reliability issue.

Since the core circuits are operated at VDD, the voltage swing of signals IN, EN, ENB is from GND to VDD. However, the voltage swing of the output signal is from GND to VCC.

Thus, the level converter is required to convert the GND-to-VDD signal to the GND-to-VCC signal in order to prevent the high-voltage overstress across the core devices. The conventional level converter co-designed with thin-oxide and thick-oxide devices is shown in Fig. 3.15, where transistors P1, P2, N1, and N2 are thick-oxide devices, but transistors P3 and N3 are thin-oxide devices. The voltage swing of signals IN and INB is from GND to VDD, whereas the voltage swing of signals OUT is from GND to VCC. If the voltage gap between VDD and VCC is too large, such conventional level converter can not be operated correctly.

Some techniques have been reported to solve this problem [49]-[52]. Using precharging devices to increase the pull-up capacity was reported in [49]. A boosting technique was reported to pump the input voltage swing of the level converter [50], [51]. The zero-Vt (or called as native-Vt) NMOS transistor was used to design the level converter for higher driving capability [52].

Due to the high-integration trend of SOC (system on a chip), a system may be integrated into a single chip. Therefore, there are digital circuits and analog circuits in a chip. For example, the digital part of a chip is designed with 1-V devices to decrease its power dissipation, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. Thus, a new output buffer is designed in a 0.13-µm 1/2.5-V CMOS process to drive 3.3-V output signals without the gate-oxide reliability issue in this section. Besides, a new level converter,

which can convert 0/1-V signals to 1/3.3-V signals, is also presented in this section.

3.2.2. Output Stage Design

Because the proposed output buffer is designed in a 0.13-µm 1/2.5-V CMOS process, the gate-to-source voltages and gate-to-drain voltages of the thin-oxide devices can not exceed 1 V. The gate-to-source voltages and gate-to-drain voltages of the thick-oxide devices can not exceed 2.5 V. However, VCC of PCI-X specification is 3.3 V [39]. Therefore, the output stage must be stacked and the gate voltages must be well controlled to prevent high-voltage overstress on their gate oxides. The new proposed output stages are shown in Figs. 3.16(a) and 3.16(b). To avoid the body effect resulting in a lower driving capacity, the

Because the proposed output buffer is designed in a 0.13-µm 1/2.5-V CMOS process, the gate-to-source voltages and gate-to-drain voltages of the thin-oxide devices can not exceed 1 V. The gate-to-source voltages and gate-to-drain voltages of the thick-oxide devices can not exceed 2.5 V. However, VCC of PCI-X specification is 3.3 V [39]. Therefore, the output stage must be stacked and the gate voltages must be well controlled to prevent high-voltage overstress on their gate oxides. The new proposed output stages are shown in Figs. 3.16(a) and 3.16(b). To avoid the body effect resulting in a lower driving capacity, the