Duty Cycle

Due to the protection devices, the duty cycle of the signal on node Din is not 50% when the mixed-voltage I/O buffer is operated in receive mode. For example, as shown in Fig. 4.10, the signal Din is not a 50%-duty-cycle signal when the 2×VDD input-tolerant mixed-voltage I/O buffer receives the 2×VDD input signal. The pulsewidth control loop circuit can be applied to adjust the duty cycle of signal Din to 50% [89], [90].

4.5. Summary

The NMOS-blocking technique has been proposed to design the mixed-voltage I/O buffer in low-voltage CMOS processes. By using the proposed NMOS-blocking technique, the mixed-voltage I/O buffer realized only with 1×VDD devices can receive 2×VDD, 3×VDD, and even 4×VDD input signals without the gate-oxide reliability issue. The 2×VDD and 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique have been successfully verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface and in a 0.13-μm 1-V CMOS process with Cu interconnects to serve 1/3-V mixed-voltage interface, respectively. The proposed NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation on the proposed NMOS-blocking technique is the pn-junction breakdown voltage of the given CMOS process.

TABLE 4.1

Fig. 4.1. Mixed-voltage I/O buffer realized with only thin-oxide devices in the mixed-voltage interface.

Fig. 4.2. An NMOS transistor, whose gate and drain are biased at VDD and 2×VDD, respectively.

Fig. 4.3. Proposed NMOS-blocking technique for mixed-voltage I/O buffer.

Fig. 4.4. 2×VDD input tolerant mixed-voltage I/O buffer by using the proposed NMOS-blocking technique.

Fig. 4.5. Dynamic gate-bias circuit in the proposed 2×VDD input tolerant mixed-voltage I/O buffer.

Fig. 4.6. Simulated waveforms of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the receive mode with 5-V input signals.

Fig. 4.7. Simulated waveforms of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the transmit mode.

Fig. 4.8. Chip photograph of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in a 0.25-µm 2.5-V CMOS process.

Fig. 4.9. Measured waveforms on the node Din and I/O pad of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the receive mode with 5-V input signals.

Fig. 4.10. Measured waveforms on the node Dout and I/O pad of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the transmit mode with 2.5-V output signals.

Fig. 4.11. 3×VDD input tolerant mixed-voltage I/O buffer by using the proposed NMOS-blocking technique.

Fig. 4.12. Dynamic gate-bias circuit in the proposed 3×VDD input tolerant mixed-voltage I/O buffer.

Fig. 4.13. Simulated waveforms of the proposed 3×VDD input tolerant mixed-voltage I/O buffer in the receive mode to receive 133-MHz 3×VDD (3-V) input signals. The waveforms are shown to observe the voltages at the nodes of I/O pad, Din, node 1, node 2, node 3, and node 4 in Fig. 4.11.

Fig. 4.14. Simulated waveforms of the proposed 3×VDD input tolerant mixed-voltage I/O buffer in the transmit mode to drive 133-MHz 3×VDD (3-V) output signals. The waveforms are shown to observe the voltages at the nodes of I/O pad, Din, node 1, node 2, node 3, and node 4 in Fig. 4.11.

Fig. 4.15. Layout of the proposed 3×VDD input tolerant mixed-voltage I/O buffer in a 0.13-µm 1-V CMOS process with Cu interconnects.

Fig. 4.16. Measured voltage waveforms of the proposed 3×VDD input-tolerant mixed-voltage I/O buffer in the receive mode to successfully receive 3×VDD (3-V) input signals.

Fig. 4.17. Measured voltage waveforms of the proposed 3×VDD input-tolerant mixed-voltage I/O buffer in the transmit mode to drive 1×VDD (1-V) output signals.

Fig. 4.18. 4×VDD input tolerant mixed-voltage I/O buffer by using the proposed NMOS-blocking technique.

Fig. 4.19. Equivalent circuit of the mixed-voltage I/O buffer designed with the proposed NMOS-blocking technique.

CHAPTER 5

Charge Pump Circuit Without Gate-Oxide Reliability Issue in Low-Voltage Processes

In this chapter, a new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit don’t exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-µm 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed 4-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD=3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process.

The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.

5.1. Background

Charge pump circuits have been often used to generate dc voltages those are higher than the normal power supply voltage (VDD) or lower than the ground voltage (GND) of the chip.

Charge pump circuits are usually applied to the nonvolatile memories, such as EEPROM or flash memories, to write or to erase the floating-gate devices [58]-[61]. In addition, charge pump circuits had been used in some low-voltage designs to improve the circuit performance [21], [62]. The 4-stage diode charge pump circuit using the pn-junction diodes as the charge transfer devices is shown in Fig. 5.1(a). The charges are pushed from the power supply (VDD) to the output node (Vout), stage by stage. Thus, the output voltage of the charge pump circuit can be pumped high. The voltage fluctuation of each pumping node can be expressed as

( )

where Vclk is the voltage amplitude of the clock signals, Cpump is the pumping capacitance, C_par is the parasitic capacitance at each pumping node, Io is output current, and f is the clock frequency. If Cpar and Io are small enough and Cpump is large enough, Cpar and Io can be ignored from equation 5.1. Because Vclk is usually with the same voltage level as the normal power supply voltage (VDD), the voltage fluctuation of each pumping node can be simply expressed as

ΔV ≈V^clk=VDD. (5.2) Hence, the output voltage of the 4-stage charge pump circuit with diodes can be expressed as

Vout 5 (VDD= ⋅ −V^D), (5.3) where VD is the cut-in voltage of the pn-junction diode. However, it is difficult to implement the fully independent diodes in the common silicon substrate. In other words, the charge pump circuit with diodes shown in Fig. 5.1(a) can not be easily integrated into the standard CMOS process. Therefore, most charge pump circuits are based on the circuit proposed by Dickson [63]-[65]. Fig. 5.1(b) shows the 4-stage Dickson charge pump circuit, where the diode-connected MOSFETs are used to transfer the charges from the present stage to the next stage. Thus, it can be easily integrated into standard CMOS processes. However, the voltage difference between the drain terminal and the source terminal of the diode-connected MOSFET is the threshold voltage when the diode-connected MOSFET is turned on.

Therefore, the output voltage of the 4-stage Dickson charge pump circuit has been derived as

5 where Vt(Mi) denotes the threshold voltage of the diode-connected MOSFET Mi. Traditionally, the bulk terminals of the diode-connected MOSFETs in the Dickson charge pump circuit are connected to ground (GND). The threshold voltage (Vt(Mi)) of the diode-connected MOSFET becomes larger due to the body effect when the voltage on each pumping node is pumped higher. Therefore, the pumping efficiency of the Dickson charge pump circuit is degraded by the body effect when the number of pumping stages is increased.

Several modified charge pump circuits based on the Dickson charge pump circuit were reported to enhance the pumping efficiency [66]-[74]. In the triple-well process, the floating-well technique [66] or the source-bulk connected devices were used to eliminate the body effect issue on the diode-connected MOSFETs in the Dickson charge pump circuit. But,

the floating-well technique may generate substrate current in the floating-well devices to influence other circuits in the same chip. The source-bulk connected technique increases the parasitic capacitance at each pumping node due to the large bulk-to-well pn-junction capacitance, so the pumping capacitors have to be enlarged. The auxiliary MOSFETs used to dynamically control the body terminals of the diode-connected MOSFETs [67] may also generate the substrate current in the floating-well devices. Four-phase clock generator was applied in the charge pump circuits to improve pumping efficiency [68]-[71], but the complex clock generator would consume more power. In [72], [73], an extra small charge pump circuit, which has more pumping stages than the main charge pump circuit, was used to control the main charge pump circuit, so the pumping efficiency of the main charge pump circuit can be enhanced. However, the charge pump circuits [72], [73] occupy larger silicon area than others because of the extra charge pump circuits. In addition, the extra small charge pump circuit consumes extra power. In [74], the charge sharing concept was used in the charge pump circuit to reduce the power consumption. However, the charge sharing concept requires the special clock generator. The 4-stage charge pump circuit reported by Wu and Chang [75] is shown in Fig. 5.2(a). The charge transfer switch (CTS) controlled by the dynamic control circuit in the Wu and Chang’s charge pump circuit is used to transfer the charges from the present stage to the next stage without suffering the limitation of threshold voltage. Fig. 5.2(b) shows the corresponding voltage waveforms of the 4-stage Wu and Chang’s charge pump circuit. When the clock signal CLK is low and the clock signal CLKB is high during the time interval T1 in Fig. 5.2(b), the voltage on node 1 is VDD and the voltage on node 2 is 3×VDD.

Because transistor MN1 is turned off and transistor MP1 is turned on, the charge transfer switch, MS1, can be completely turned on to transfer charges from the power supply (VDD) to node 1. During the time interval T2, the voltage on node 2 can be pumped as high as 2×VDD to turn on transistor MN1 and to turn off transistor MP1. Thus, the charge transfer switch, MS1, can be completely turned off to prevent the charges back to the power supply (VDD). The operation of next stages in Wu and Chang’s charge pump circuit is similar to that of the first stage. Because the CTS’s can be completely turned on or turned off by the dynamic control circuits, the pumping efficiency has been enhanced with ideal output voltage of 5×VDD. However, the output stage (MDO) of Wu and Chang’s charge pump circuit is still a diode-connected MOSFET, so it also suffers the body effect issue. Besides, because the maximum voltage difference of each stage is 2×VDD, all devices of Wu and Chang’s charge pump circuit suffer the high-voltage overstress on their gate oxides.

With the advanced CMOS processes, the thickness of the gate oxide becomes thinner so

the operation voltage of transistor must be lowered due to the reliability issue [1]. Thus, the gate-oxide reliability issue [76] must be also considered into the design of charge pump circuits, especially in the low-voltage CMOS processes. In this chapter, a new charge pump circuit that has better pumping efficiency but without the gate-oxide reliability issue in low-voltage processes is presented [77]. The new proposed charge pump circuit has been successfully verified in a 0.35-µm 3.3-V CMOS process.

5.2. New Charge Pump Circuit Without Gate-Oxide Reliability Issue

The circuit and the corresponding voltage waveforms of the new proposed charge pump circuit with 4 stages are shown in Figs. 3(a) and 3(b), respectively. To avoid the body effect, the bulks of the devices in the proposed charge pump circuit are recommended to be connected to their sources respectively if the given process provides the deep n-well layer.

Clock signals CLK and CLKB are out-of-phase but with the amplitudes of VDD. As shown in Fig. 5.3(a), there are two charge transfer branches, branch A and branch B, in the new proposed charge pump circuit. Branch A is comprised of transistors MN1, MN2, MN3, MN4, MP1, MP2, MP3, and MP4 with the capacitors C1, C2, C3, and C4. Branch B is comprised of transistors MN5, MN6, MN7, MN8, MP5, MP6, MP7, and MP8 with the capacitors C5, C6, C7, and C8. The control signals of branches A and B are intertwined. Besides, clock signals of branches A and B are out-of-phase. When the clock signals of the first and the third pumping stages in the branch A are CLK, those in the branch B are CLKB. Similarly, when the clock signals of the second and the forth pumping stages in the branch A are CLKB, those in the branch B are CLK. Thus, branches A and B can see as two independent charge pump circuits but their output nodes are connected together. Because the clock signals of the branch A and those of the branch B are out-of-phase, the voltage waveforms of nodes 1-4 and those of nodes 5-8 are also out-of-phase. Hence, branches A and B can pump the output voltage to high, alternately. The detailed operations of the new proposed charge pump circuit are described below.

As illustrated in Fig. 5.3(b), the clock signal CLK is low and the clock signal CLKB is high during the time interval T1. At this moment, the voltage difference (V15) between node 1 and node 5 is –VDD. Therefore, transistor MN1 is turned on to transfer the charges from the power supply (VDD) to node 1, but the transistor MN5 is turned off to cut off the path from

node 5 back to the power supply. Similarly, V15 becomes VDD during the time interval T2.

Transistor MN1 is turned off to cut off the leakage path from node 1 back to the power supply, but the transistor MN5 is turned on to transfer the charges from the power supply to node 5.

In the second stage, when the clock signal CLK is low and the clock signal CLKB is high during the time interval T1, V15 and the voltage difference (V26) between node 2 and node 6 are –VDD and VDD, respectively. Therefore, transistors MP5 and MN6 are turned on to transfer the charges from node 5 to node 6, but transistors MP1 and MN2 are turned off to cut off the path from node 2 back to node 1. Similarly, V15 and V26 are VDD and –VDD during the time interval T2, respectively. Transistors MP5 and MN6 are turned off in order to cut off the path from node 6 back to node 5, but transistors MP1 and MN2 are turned on to transfer the charges from node 1 to node 2. The operation of the third pumping stage is similar to that of the second pumping stage.

As shown in Fig. 5.3(a), the output nodes of braches A and B are connected together.

When the clock signal CLK is low and the clock signal CLKB is high during the time interval T1, the voltage difference (V48) between node 4 and node 8 is VDD. Therefore, transistor MP4 is turned on to transfer the charges from node 4 to the output node, but transistor MP8 is turned off to cut off the path from the output node back to node 8. On the other hand, V48

is –VDD during the time interval T2. Hence, the transistor MP4 is turned off and the current path from the output node back to node 4 is cut off. In addition, the transistor MP8 is turned on to transfer the charges from node 8 to the output node.

As shown in Fig. 5.3 (b), the gate-source voltages (Vgs) and gate-drain voltages (Vgd) of all MOSFETs in the new proposed charge pump circuit do not exceed VDD. Thus, there is no high-voltage overstress on the gate oxide of the devices in the new proposed charge pump circuit.

5.3. Verifications and Discussions

5.3.1. Simulation Results and Comparisons

A 0.18-µm 1.8-V CMOS device model is used to verify the design of the new proposed charge pump circuit in HSPICE simulation. Fig. 5.4 shows the simulated voltage waveforms of the new proposed 4-stage charge pump circuit with each pumping capacitor of 1 pF and

5-µA output current. The expected waveforms shown in Fig. 5.3(b) are similar to the simulated waveforms shown in Fig. 5.4. Ideally, the output voltage of the new proposed 4-stage charge pump circuit with 1.8-V power supply voltage (VDD=1.8 V) should be as high as 9 V (1.8×5=9). However, due to the parasitic capacitance at each pumping node and the loading of the output current, the simulated output voltage of the new proposed charge pump circuit is around 8.39 V.

Fig. 5.5 shows the simulated output voltages of the proposed charge pump circuit under different output currents and power supply voltages (VDD). When the output current is increased, the output voltages of the proposed charge pump circuit under different power supply voltages (VDD) are decreased. If the new proposed charge pump circuit only drives the capacitive load, the output voltages of the proposed charge pump circuit under different power supply voltages (VDD) are close to 5×VDD. If the supply voltage is too low and the output current is too high, the proposed charge pump circuit can not pump the output voltage high.

The simulated output voltages of the Dickson charge pump circuit [63], Wu and Chang’s charge pump circuit [75], and the new proposed charge pump circuit with different output currents are compared in Fig. 5.6. Actually, the pumping capacitors of a charge pump circuit take a great part in silicon area. For fair comparison, the total pumping capacitors of these charge pump circuits must be equaled. Therefore, the pumping capacitors in the proposed charge pump circuit, in Wu and Chang’s charge pump circuit, and in the Dickson charge pump circuit are set to 1 pF, 1.6 pF (1×8/5=1.6), and 2 pF (1×8/4=2), respectively. As shown in Fig. 5.6, the output voltages of the proposed charge pump circuit with different output currents are much higher than those of other charge pump circuits. Especially, with the higher output current of 30 μA, the proposed charge pump circuit still has the better pumping performance than others. Since the proposed charge pump circuit has two pumping branches pushing the charges to the output node alternately, the degradation of the output voltage is smaller while the output current increases. Besides, the MOSFET switches in the new proposed charge pump circuit are fully turned on to transfer the charges, but all MOSFET switches in the Dickson charge pump circuit and the output stage of Wu and Chang’s charge pump circuit are diode-connected transistors, which have the threshold voltage drop problem.

Therefore, the proposed charge pump circuit has better pumping performance than others, as shown in Fig. 5.6.

Fig. 5.7 compares the simulated output voltages of the Dickson, Wu and Chang’s, and the new proposed charge pump circuits under different power supply voltages (VDD) without

output current loading. As shown in Fig. 5.7, the output voltages of these three charge pump circuits are degraded when the power supply voltage is decreased. However, the new proposed charge pump circuit still has higher output voltages under the lower power supply voltage because the proposed charge pump circuit has better pumping efficiency. Thus, the proposed charge pump circuit is more suitable in low-voltage processes than the prior designs.

Branches A and B in the new proposed charge pump circuit can pump the output voltage

Branches A and B in the new proposed charge pump circuit can pump the output voltage