Discussions and Comparisons

2.5.1. Speed

The output loadings of these mixed-voltage I/O buffers include the I/O pad, the bonding wire, the package pin, the PCB trace, and so on. Therefore, the output loadings of these I/O buffers are usually very large. These mixed-voltage I/O buffers are simulated in a 0.25-µm 2.5-V CMOS process to compare their speed performances under the condition of the same output loading. Table 2.1 shows the simulated delay times from the node Dout to the I/O pad when these I/O buffers are in the transmit mode to drive a 20-pF output loading. As shown in Table 2.1, the delay times of these I/O buffers in Figs. 2.6, 2.7, 2.8, 2.9, and 2.13 are almost the same, expect those of the I/O buffers in Figs. 2.4 and 2.5. Although the driving capacities (by adjusting the device dimensions of output transistors) and the output capacitances of these I/O buffers are kept the same, the parasitic capacitances of the stacked PMOS devices in the output stage of the mixed-voltage I/O buffers in Figs. 2.4 and 2.5 are large. Besides, the larger threshold voltage of transistor MP0 in Fig. 2.4 (Fig. 2.5) owing to the body effect results in the lower driving capacity. Thus, these two I/O buffers in Figs. 2.4 and 2.5 have a little longer delay times than the other mixed-voltage I/O buffers.

2.5.2. Power Consumption

The power consumption of CMOS digital circuit includes three parts: the dynamic power consumption due to charging and discharging the capacitance, the short-circuit power

consumption, and the power consumption due to the dc leakage current. Because there should be no dc leakage current in the design of these mixed-voltage I/O buffers whenever they operate in the receive mode or transmit mode, the power consuming on the output loading dominates the total power consumption in these I/O buffers. Hence, the power consumptions of these mixed-voltage I/O buffers are almost the same if the output loadings are kept the same and the operating frequency is fixed. These mixed-voltage I/O buffers are simulated in a 0.25-µm 2.5-V CMOS process. The simulated power consumptions of these mixed-voltage I/O buffers in the transmit mode to drive the 20-pF output loading at the frequency of 50 MHz are compared in Table 2.2. Although the output loadings of these mixed-voltage I/O buffers are all the same of 20 pF, the power consumptions of the I/O buffers in Figs. 2.4 and 2.5 are somewhat larger than those of the other I/O buffers. The reason is that the parasitic self output capacitances of the mixed-voltage I/O buffers in Figs. 2.4 and 2.5 are larger than those of the other I/O buffers.

2.5.3. Area

The total area of these mixed-voltage I/O buffers can be evaluated by calculating the total channel widths of transistors in these I/O buffers if the channel lengths of all devices in these I/O buffers are kept the same. Table 2.3 shows the calculated total widths of these mixed-voltage I/O buffers, where Wp and Wn are the unit width of the PMOS and NMOS devices, respectively. The total width is calculated including the widths of the devices in the pull-up and pull-down paths, the dynamic n-well bias circuit, the gate-tracking circuit, and the protecting devices of input buffer. Expect the devices in the pull-up and pull-down paths, the widths of the PMOS and NMOS devices in these I/O buffers are kept as Wp and Wn, respectively. For fair comparison, the driving capacities of the output stages in these mixed-voltage I/O buffers must be kept the same. Therefore, the widths of the PMOS and NMOS devices in the output stage of stacked configuration are twice as those in the output stage of single device. In this calculation, the widths of the PMOS and NMOS devices in the output stage of single device are 3Wp and 3Wn, respectively. The widths of the PMOS and NMOS devices in the output stage of stacked configuration are 6Wp and 6Wn, respectively.

Generally, Wp is triple as large as Wn in CMOS digital circuits [35]. Hence, the total widths of these mixed-voltage I/O buffers can be shown in terms of Wn for comparison. As shown in Table III, the total widths of the proposed mixed-voltage I/O buffers 1 and 2 are 37Wn and

42Wn, respectively. Although the total width of the I/O buffer in Fig. 2.6 is 19Wn, this I/O buffer needs an extra pad to provide the external voltage to bias the n-well of the pull-up PMOS device. The area of this I/O buffer in Fig. 2.6, when it includes the extra pad into the chip, will become larger than that of the proposed I/O buffers.

2.5.4. Noise, Latch-Up, and Subthreshold Leakage Issues

The n-wells of the pull-up PMOS devices in some mixed-voltage I/O buffers will be floated in some operation conditions. The I/O coupling noise into the floating n-wells of the pull-up PMOS devices could induce the latch-up issue. Therefore, the pull-up PMOS devices in these mixed-voltage I/O buffers must be carefully drawn in the layout. The guard rings must be used to surround the pull-up PMOS devices to isolate the I/O noise against the latch-up problem [36]. In addition, the lower threshold voltage of the pull-up PMOS device due to the lower floating n-well voltage results in the subthreshold leakage current. The proposed mixed-voltage I/O buffer 2 and the prior design [25] don’t have the floating n-well issue. Thus, these two mixed-voltage I/O buffers are suitable for low-power applications.

2.5.5. Transient Stress

The stacked NMOS technique is used avoid the gate-oxide overstress in the mixed-voltage I/O interface, as shown in Fig. 2.3. However, in some specified operation state, the upper transistor (MN0) may still suffer the hot-carrier issue. When the voltage on the I/O pad is initially kept at 5 V and then the transistor MN1 in Fig. 2.3 is turned on by its pre-driver circuit to pull down the pad voltage to 0 V, the drain-source voltage of transistor MN0 may exceed 2.5 V during this transient condition to suffer the hot-carrier degradation.

Nevertheless, this transient-stress problem can be further solved by using three stacked devices and dynamically controlling the gate voltage of the top device [15].

2.5.6. Comparisons

Table 2.4 lists the features among these mixed-voltage I/O buffers. Since the new proposed mixed-voltage I/O buffers and the prior I/O buffers reported in [24], [25], [33], and

[34] use the dynamic n-well biased technique, no extra pad and power supply is required. The new proposed mixed-voltage I/O buffers in this work occupy smaller silicon area than the I/O buffers reported in [23]-[25], [33], [34]. Although the circuit structures of the mixed-voltage I/O buffers reported in [33], [34] are simpler, these two I/O buffers have the gate-oxide reliability problem. In Fig. 2.4, transistors MN0, MN1, and MP2 have the gate-oxide reliability problem in the tri-state input mode when the input signal has a 5-V voltage level.

In Fig. 2.5, transistor MP2 has the gate-oxide reliability problem when the input signal at the I/O pad is 5 V in the tri-state mode. Besides, since the depletion PMOS is used to improve the gate-tracking circuit of the mixed-voltage I/O buffer reported in [23], extra mask and process modification are required to realize the depletion device. The prior mixed-voltage I/O buffers reported in [24], [33], [34] and the proposed mixed-voltage I/O buffer 1 may have the subthreshold leakage problem, but the prior mixed-voltage I/O buffer reported in [25] and the proposed mixed-voltage I/O buffer 2 don’t have. However, the proposed mixed-voltage I/O buffers occupy smaller silicon area than the prior I/O buffers [24], [25], [33], [34]. Thus, if the subthreshold leakage issue in the given CMOS process is not serious, the proposed mixed-voltage I/O buffer 1 is more recommended than the prior designs reported in [24], [33], [34]. If the subthreshold leakage problem in the given CMOS problem is serious, such as the 0.13-µm, 90-nm or below CMOS process, the proposed mixed-voltage I/O buffer 2 is recommended.