Output Buffer

3.2.1. Background

The thickness of gate oxide becomes thinner in order to decrease the core power supply voltage (VDD) as the semiconductor technology is scaled down [1]. This results in lower power consumption. However, the board voltage (VCC) is still kept as high as 3.3 V (or 5 V), such as PCI-X interface [39]. There are three problems on a MOSFET when the operating voltage is higher than its normal voltage. Higher drain-to-source voltage (Vds) may cause the serious hot-carrier effect which results in the long-term lifetime issue [6]. The drain-to-bulk

pn-junction breakdown may occur if the operating voltage is too high. The high-voltage overstress across the thinner gate oxide could also destruct the gate oxide [27], [28].

Therefore, the I/O circuits must be designed carefully to overcome these problems, especially the high-voltage gate-oxide overstress [23]-[26].

Recently, the dual-oxide (thin-oxide and thick-oxide) processes have been supported by some manufacturing companies [32], [47], [48]. For example, the thin-oxide devices are 1-V or 1.2-V devices and the thick-oxide devices are 1.8-V, 2.5-V, or 3.3-V devices in a 0.13-µm CMOS process [47], [48]. The thin-oxide devices are used to design the digital circuits to decrease silicon area and power consumption. The thick-oxide devices are used to design the analog circuits to improve circuit performance or the I/O circuits to avoid the gate-oxide reliability issue. Fig. 3.14 shows the conventional tri-state I/O buffer co-designed with thin- and thick-oxide devices. As shown in Fig. 3.14, transistors P1 and N1 are the thick-oxide devices, which can sustain the voltage level of VCC to avoid the gate-oxide reliability issue.

Since the core circuits are operated at VDD, the voltage swing of signals IN, EN, ENB is from GND to VDD. However, the voltage swing of the output signal is from GND to VCC.

Thus, the level converter is required to convert the GND-to-VDD signal to the GND-to-VCC signal in order to prevent the high-voltage overstress across the core devices. The conventional level converter co-designed with thin-oxide and thick-oxide devices is shown in Fig. 3.15, where transistors P1, P2, N1, and N2 are thick-oxide devices, but transistors P3 and N3 are thin-oxide devices. The voltage swing of signals IN and INB is from GND to VDD, whereas the voltage swing of signals OUT is from GND to VCC. If the voltage gap between VDD and VCC is too large, such conventional level converter can not be operated correctly.

Some techniques have been reported to solve this problem [49]-[52]. Using precharging devices to increase the pull-up capacity was reported in [49]. A boosting technique was reported to pump the input voltage swing of the level converter [50], [51]. The zero-Vt (or called as native-Vt) NMOS transistor was used to design the level converter for higher driving capability [52].

Due to the high-integration trend of SOC (system on a chip), a system may be integrated into a single chip. Therefore, there are digital circuits and analog circuits in a chip. For example, the digital part of a chip is designed with 1-V devices to decrease its power dissipation, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. Thus, a new output buffer is designed in a 0.13-µm 1/2.5-V CMOS process to drive 3.3-V output signals without the gate-oxide reliability issue in this section. Besides, a new level converter,

which can convert 0/1-V signals to 1/3.3-V signals, is also presented in this section.

3.2.2. Output Stage Design

Because the proposed output buffer is designed in a 0.13-µm 1/2.5-V CMOS process, the gate-to-source voltages and gate-to-drain voltages of the thin-oxide devices can not exceed 1 V. The gate-to-source voltages and gate-to-drain voltages of the thick-oxide devices can not exceed 2.5 V. However, VCC of PCI-X specification is 3.3 V [39]. Therefore, the output stage must be stacked and the gate voltages must be well controlled to prevent high-voltage overstress on their gate oxides. The new proposed output stages are shown in Figs. 3.16(a) and 3.16(b). To avoid the body effect resulting in a lower driving capacity, the bulks of the transistors in Figs. 3.16(a) and 3.16(b) are connected to their sources individually.

In Fig. 3.16(a), the pull-up path and pull-down path have two stacked 2.5-V PMOS transistors (P1 and P2) and 2.5-V NMOS transistors (N1 and N2), respectively. Since the gate voltages of transistors P2 and N2 are biased at VDD (1 V), the extra bias generator is not required. Because the gate voltages of transistors P2 and N2 are biased at 1 V, the gate-to-source voltages (Vgs) and the gate-to-drain voltages (Vgd) of transistors P2 and N2 don’t exceed 2.5 V. The maximum Vgs and Vgd of transistors P2 and N2 are around 2.3 V (3.3−1=2.3). Transistors P2 and N2 are used to protect transistors P1 and N1 against the high-voltage gate-oxide overstress, respectively. However, the source voltage of transistor P1 is 3.3 V. In this design, the minimum voltage level of signal PU can’t be lower than 0.8 V (3.3−2.5=0.8). The voltage swing of signal PU can be designed between 1 V (VDD) to 3.3 V (VCC) to control the gate of transistor P1. Hence, a level converter that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is demanded for the proposed output buffer.

In Fig. 3.16(a), transistors N1 and N2 are 2.5-V normal-Vt NMOS transistors with threshold voltage of 0.6 V, which is still too high for high speed operation when the Vgs of the normal-Vt NMOS transistor is only 1 V. Hence, the driving capability of the pull-down path in Fig. 3.16(a) needs to be improved. Therefore, a modified version of output stage is shown in Fig. 3.16(b). Transistor N2 in Fig. 3.16(b) is a 2.5-V native-Vt NMOS transistor, which has a threshold voltage of −0.1 V. Transistor N1 in Fig. 3.16(b) is a 1-V NMOS transistor. The native-Vt NMOS transistor is one of standard devices in a 0.13-µm CMOS process without extra process modification [47]. Therefore, the driving capability of the output buffer in Fig. 3.16(b) can be increased. Because the gate of transistor N2 is biased at 1

V, transistor N1 in Fig. 3.16(b) can be safely operated without suffering high-voltage gate-oxide overstress. However, since transistor N2 is a native-Vt NMOS transistor, the sub-threshold leakage current could be serious. If the voltage on node OUT in Fig. 3.16(b) is 3.3 V, the sub-threshold current of transistor N2 may occur. Thus, the voltage on node A in Fig. 3.16(b) may exceed 1 V. An extra PMOS transistor P3 is added in Fig. 3.16(b) to keep the maximum voltage on node A at 1 V. When signals PU and PD are at logic “0” (1 V and 0 V), the voltage on node OUT is VCC (3.3 V). Because signal PD is at 0 V, transistor P3 is turned on to keep the voltage on node A at 1 V. Hence, the high-voltage gate-oxide overstress caused by sub-threshold leakage of transistor N2 can be avoided. Because transistor P3 is a weak device that keeps the voltage on node A at 1 V, it can be a 2.5-V normal-Vt PMOS transistor. Fig. 3.17 shows the simulated waveforms of the output stages in a 0.13-µm CMOS process with 1-V and 2.5-V devices. In this simulation, the transistor sizes of these two output stages are kept the same. As shown in Fig. 3.17, the driving (pull-down) speed of the output stage in Fig. 3.16(b) is better than that of the output stage in Fig. 3.16(a).

3.2.3. Level Converter Design

Fig. 3.18 shows the new proposed level converter that can convert 0/1-V voltage swing to 1/3.3-V voltage swing. In Fig. 3.18, the bulks of the transistors are connected to their sources, respectively, because of the body effect issue. Transistors N1A and N1B are 1-V normal-Vt NMOS transistors, whereas transistors N2A and N2B are 2.5-V native-Vt NMOS transistors, so the driving capability can be increased. The other transistors are all 2.5-V normal-Vt transistors. Transistors P3A can keep the voltage on node A1 at 1 V when the voltage on node B1 is 3.3 V. Similarly, transistor P3B is used to keep the voltage on node A2 at 1 V when the voltage on node B2 is 3.3 V. The voltage swing of input signals IN and INB is from 0 V to 1 V. When signal IN is 1 V and signal INB is 0 V, the voltage on node B1 is pulled down to 0 V and transistor P5A is turned on. After transistor P5A is turned on, the voltage on node OUTB is pulled down to 1 V, and then transistors P4B and P1B are turned on.

Therefore, the voltages on nodes OUT and B2 are both pulled up to 3.3 V.

When signal IN is 0 V and signal INB is 1 V, the voltage on node B2 is pulled down to 0 V and transistor P5B is turned on. After transistor P5B is turned on, the voltage on node OUT is pulled down to 1 V, and then transistors P4A and P1A are turned on. Therefore, the voltages on nodes OUTB and B1 are both pulled up to 3.3 V.

Because using PMOS transistors to pull down nodes OUT and OUTB could be too slow, two cross-coupled NMOS transistors N3A and N3B are added to increase the pull-down speed. Fig. 3.19 shows the simulated waveforms of the new proposed level converter in a 0.13-µm 1/2.5-V CMOS process. The pull-down speed of the proposed level converter with transistors N3A and N3B is faster than that of the level converter without N3A and N3B.

3.2.4. Whole Output Buffer Design

Fig. 3.20 depicts the whole output buffer, which consists of an output stage, a level converter, a tri-state control circuit, and two kinds of taper buffers (taper buffer 1 and taper buffer 2). In Fig. 3.20, a CMOS NAND gate and a NOR gate are used to implement the tri-state control circuit. When control signal EN is 0 V and control signal ENB is 1 V, the output buffer is in the high-impendence state. When control signal EN is 1 V and control signal ENB is 0 V, the output buffer drives the output pad according to the signal IN from the core circuits. Fig. 3.21(a) shows another tri-state control circuit, which consists of only six transistors [24]. Compared with the traditional tri-state control circuit in Fig. 3.20, the circuit in Fig. 3.21(a) may have the smaller silicon area and input capacitance. Thus, the tri-state control circuit in Fig. 3.21(a) can be used to replace the traditional tri-state control circuit in Fig. 3.20. The output stage of this whole output buffer is the same as that in Fig. 3.16(b). The level converter that can transfer the signal swing from 0/1 V to 1/3.3 V has been shown in Fig.

3.18. Taper buffer 1 and taper buffer 2 are demanded to drive the output stage because the transistors in the output stage are large-size devices. Because the voltage swing of signal PU is from 1 V to 3.3 V, the INV1 in taper buffer 1 is shown in Fig. 3.21(b). The PMOS and NMOS transistors of INV1 are 2.5-V normal-Vt devices. Because the voltage swing of signal PD is from 0 V to 1 V, the INV2 in taper buffer 2 is shown in Fig. 3.21(c), where the PMOS and NMOS transistors of INV2 are 1-V normal-Vt transistors. In order to keep the signal PU and signal PD in phase, the delay of taper buffer 1 and level converter must be adjusted equal to that of taper buffer 2. In Fig. 3.21, the bulks of the transistors are connected to their sources, respectively, because of the body effect.

Fig. 3.22 shows the simulated waveforms on nodes IN, OUT, PU, and PD in the proposed output buffer with a 133-MHz 3.3-V output signal in a 0.13-μm 1/2.5-V CMOS process. The output load is 10 pF in this simulation. Because the parasitic inductance (15 nH) of the bond wire is also included in this simulation, the overshooting and undershooting of

the output waveform can be found in Fig. 3.22. Table 3.1 summarizes the other simulation results of the proposed output buffer. The delay times are measured from the input signal (IN) of 0.5×VDD (0.5-V) voltage level to the output signal (OUT) of 0.5×VCC (1.65-V) voltage level. As shown in Table 3.1, the simulated rising delay time (Td-rising) and falling delay time (Td-falling) are 1.15 ns and 1.08 ns, respectively. The output rising time (Trising) and falling time (Tfalling) are defined form 0.1×VCC (0.33 V) to 0.9×VCC (2.97 V) and from 0.9×VCC (2.97 V) to 0.1×VCC (0.33 V), respectively. As shown in Table 3.1, the simulated Trising and Tfalling

are 0.85 ns and 0.73 ns, respectively. The output low current (IOL) is defined when the output voltage is at 0.1×VCC (0.33 V). The output high current (IOH) is defined when the output voltage is at 0.9×VCC (2.97 V). As shown in Table 3.1, the simulated IOL and IOH are 59.3 mA and 39.4 mA, respectively. The simulated power consumption is 29.77 mW when the proposed output buffer is operated in 133 MHz with 10-pF load at the pad. In this simulation, the proposed output buffer successfully drives the I/O pad according to the input signal IN.

3.2.5. Experimental Results

The proposed output buffer has been fabricated in a 0.13-µm 1/2.5-V 1P8M CMOS process with Cu interconnects. Fig. 3.23 shows the layout of the proposed output buffer. The layout area of the proposed output buffer is around 125 μm × 253 µm. Besides, the testchip also includes the stand-alone level converter to verify its logic functions and voltage levels.

Fig. 3.24 shows the measured waveforms of the new proposed level converter. As shown in Fig. 3.24, the proposed level converter can successfully transfer the voltage swing from 0/1 V to 1/3.3 V. Fig. 3.25 shows the measured waveforms of the proposed output buffer operating with a 133-MHz 3.3-V output signal. As shown in Fig. 3.25, the proposed output buffer can successfully drive the output pad without gate-oxide overstress. Besides, the measured IOL

and IOH of the proposed output buffer are 69.2 mA and 44.1 mA, respectively. Due to process variation, the measured IOL and IOH are slightly different from the simulated IOL and IOH.

3.2.6. Discussions

The hot-carrier degradation and the drain-to-bulk breakdown issues are the other reliability issues in the high-voltage-tolerant circuits. To avoid the hot-carrier degradation, the drain-to-source voltage (Vds) of the device operated in the saturation region can not be higher

than the normal operating voltage [6]. For example, the Vds of the 1-V (2.5-V) device can not be higher than 1 V (2.5 V). The maximum Vds of 1-V devices and 2.5-V devices in the proposed output buffer are about 1 V and 2.3 V, respectively. Thus, the proposed output buffer not only considers the gate-oxide reliability issue but also the hot-carrier degradation issue. In general, the drain-to-bulk breakdown voltage is at least as twice as the normal operating voltage in the standard CMOS process [47], [48]. Hence, the drain-to-bulk breakdown issue can be ignored in the proposed output buffer.

3.2.7. Summary

An output buffer realized with low-voltage devices to drive high-voltage output signals is presented in this section. The proposed output buffer has been fabricated in a 0.13-μm 1/2.5-V CMOS process to drive 3.3-V signals without suffering high-voltage gate-oxide overstress. The experimental results have shown that the proposed output buffer can be successfully operated with a 133-MHz 3.3-V output signal. Moreover, a new level converter, which can convert the 0/1-V signal swing to 1/3.3-V signal swing, has been also verified in this section. The proposed output buffer and level converter are suitable for mixed-voltage interface applications in the nanometer CMOS processes.