Chapter 6. Ultra-High-Voltage Charge Pump Circuit With Polysilicon Diodes
6.3. Ultra-High-Voltage Charge Pump Circuit
6.3.1. Circuit Implementation
Fig. 6.6 depicts the 4-stage charge pump circuit designed with 5 polysilicon diodes (PD1~PD5), where the clock signals, CLK and CLKB, are out-of-phase with the amplitudes of VDD. RL and CL in Fig. 6.6 represent the output loading of resistance and capacitance, respectively. CL can make the output voltage of the charge pump circuit more stable. As shown in Fig. 6.6, the charge pump circuit uses the polysilicon diodes as the charge transfer devices. The charges are pushed from the power supply (VDD) to the output node (Vout) stage by stage every clock cycle. The voltage fluctuation between each stage can be expressed as
( )
where Vclk is the voltage amplitude of the clock signals, CLK and CLKB, Cpump is the pumping capacitance, Cpar is the parasitic capacitance at each pumping node, Io is output current, and f is the clock frequency. The output voltage of the charge pump circuit can be expressed as
Vout (VDD V ) n (= − D + ⋅ Δ −V V )D , (6.2) where VD is the cut-in voltage of the polysilicon diode and n is the number of stages in the charge pump circuit. If Cpar and Io are small enough and Cpump is large enough, Cpar and Io can be ignored in equation 6.1. Because Vclk is usually with the same voltage level as the normal power supply voltage (VDD), the voltage fluctuation between each stage can be simply expressed as
VDD V Vclk
Δ ≈ = . (6.3) Hence, equation 6.2 can be simplified as
Vout (n 1) (VDD V )= + ⋅ − D . (6.4) The power efficiency of the charge pump circuit is defined as
Efficiency = Vout In equation 6.5, IVDD is the total current flows from the power supply (VDD). IVDD can be derived as [86]
Thus, equation 6.6 can be substituted in equation 6.5. The power efficiency of the charge pump circuit can be easily calculated.
6.3.2. Experimental Results
The 4-stage, 8-stage, and 12-stage charge pump circuits with 10-pF on-chip (MIM) pumping capacitors and the polysilicon diodes of 0.5-µm and 1-µm un-doped region have been fabricated in a 0.25-µm 2.5-V bulk CMOS process. The photograph of the 4-stage charge pump circuit realized with 5 polysilicon diodes (Lc=0.5 µm) is shown in Fig. 6.7. The independent polysilicon diodes with different lengths of the un-doped region are also implemented in this testchip.
Fig. 6.8 shows the measured waveforms of the 12-stage charge pump circuit with the polysilicon diodes (Lc=0.5 µm) to drive the capacitive output load. In Fig. 6.8, the power supply voltage (VDD) and the amplitude of the clock signals (CLK and CLKB) are 2.5 V, and the clock frequency is 1 MHz. As shown in Fig. 6.8, the output voltage of the charge pump circuit to drive the capacitive load is as high as 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in the given 0.25-µm 2.5-V bulk CMOS process.
Fig. 6.9 shows the measured output voltages of the 4-stage, 8-stage, and 12-stage charge pump circuits with the polysilicon diodes of 0.5-µm or 1-µm un-doped region (Lc). In Fig.
6.9, the proposed charge pump circuits drive only the capacitive loads with the clock frequency of 1 MHz and the power supply voltage (VDD) of 2.5 V. As shown in Fig. 6.9, the measured output voltages of the proposed charge pump circuits with the polysilicon diodes (Lc=0.5 or 1 µm) are almost the same. The length of the un-doped region (Lc) doesn’t obviously affect the output voltage of the proposed charge pump circuit because the voltage across each polysilicon diode doesn’t exceed VDD (2.5 V), which is much smaller than the reverse breakdown voltages of the polysilicon diodes (Lc=0.5 or 1 µm).
Fig. 6.10 shows the measured output voltages of the 4-stage charge pump circuit with the polysilicon diodes (Lc=1 µm) under different clock frequencies, where the power supply voltage (VDD) is 2.5 V. When the clock frequency is increased, the output voltages of the charge pump circuit are also increased. But, when the clock frequency is low, the output voltages of the charge pump circuit are degraded, especially with a small RL. In Fig. 6.10, the charge pump circuit can pump the output voltage close to the ideal value in equation 6.4 when the RL is large and the clock frequency is high.
Fig. 6.11 compares the measured output voltages of the 4-stage charge pump circuits with the polysilicon diodes of 0.5-µm and 1-µm un-doped region under different power supply voltages (VDD). In Fig. 6.11, the charge pump circuits drive only the capacitive loads, and the clock frequency is 100 kHz. As shown in Fig. 6.11, the polysilicon diode with long length (Lc=1 µm) can generate a higher output voltage level than that with short length (Lc=0.5 µm) As the power supply voltage (VDD) is higher than the breakdown voltage of the polysilicon diode with 0.5-μm un-doped region but still lower than that of the polysilicon diode with 1-μm un-doped region, the charge pump circuit with the polysilicon diode of 1-μm un-doped region still pumps the output voltage higher, but the output voltage of the charge pump circuit with the polysilicon diode of 0.5-μm un-doped region is degraded.
Fig. 6.12 shows the measured output voltage of the 4-stage charge pump circuit (Lc=1 µm) with the output resistors of 1 MΩ, 10 MΩ, and without the output resistor when the clock frequency is 100 kHz. As shown in Fig. 6.13, the output voltage is degraded when the RL is small.
6.3.3. Discussions
Table 6.1 compares the polysilicon diode (this work), pn-junction diode, MOS diode (Dickson) [63] charge pump circuits. The voltage fluctuations between each stage in the polysilicon diode, pn-junction diode, and MOS diode (diode-connected MOS) charge pump circuits are VDD–VD-P, VDD–VD-PN, and VDD–Vt, respectively. VD-P and VD-PN are the cut-in voltages of the polysilicon and pn-junction diodes, respectively, and Vt is the threshold voltage of the MOS diode.
However, Vt increases due to the body effect as the number of stages increases. The power efficiencies of the polysilicon diode, pn-junction diode, MOS diode charge pump circuits only depends on the parasitic capacitance (Cpar) at each stage if the charge pump circuits are applied with the same number (n) of stages, the same pumping capacitance (Cpump), and the same clock frequency (f) [87]. The parasitic capacitance of the polysilicon diode has been discussed in [88]. The parasitic capacitance of the polysilicon diode is smaller than other, because the polysilicon diode is formed on the STI layer, the pn-junction diode has larger parasitic capacitance between n-well and p-substrate, and the MOS diode has larger gate capacitance. Thus, the power efficiency of the polysilicon diode chare pump circuit is better than others. The area of the charge pump circuit is dominated by the on-chip pumping capacitors, so these three kinds of the charge pump circuits occupy almost the same chip area with the same pumping capacitors and the same number (n) of the stages. As described in the previous section, the output voltages of the pn-junction diode and MOS diode charge pump circuits are limited by the parasitic pn-junctions, but that of the polysilicon diode charge pump circuit isn’t.
6.4. Summary
An ultra-high-voltage charge pump circuit realized with the polysilicon diodes has been
successfully verified in a 0.25-µm 2.5-V bulk CMOS process. The polysilicon diodes are implemented on the STI layer, which are fully isolated from the silicon substrate. Therefore, the maximum output voltage of the proposed charge pump circuit with the polysilicon diodes isn’t limited by the junction breakdown voltage. In addition, the polysilicon diodes are fully compatible to the bulk CMOS processes without any extra process modification. The 4-stage, 8-stage, and 12-stage charge pump circuits with 10-pF on-chip pumping capacitors and the polysilicon diodes of 0.5-µm and 1-µm un-doped center region have been fabricated in a 0.25-µm 2.5-V bulk CMOS process. To drive the capacitive load, the measured results show that the 4-stage charge pump circuit with the polysilicon diodes (Lc=0.5 µm) can pump the output voltage as high as 28.08 V, whereas the power supply voltage (VDD) is 2.5 V. The output loading effect and the dependence of clock frequency on the output voltage of the proposed charge pump circuit have been also measured. The proposed scheme can be applied to the ultra-high-voltage applications, such as MEMS or electroluminescent displays.
TABLE 6.1
SUMMARY OF THE POLYSILICON DIODE (THIS WORK), PN-JUNCTION DIODE,MOSDIODE
CHARGE PUMP CIRCUITS
Voltage Fluctuation
Power Efficiency
Area Output Voltage Limitation
Polysilicon diode VDD–VD-P Better Same No
pn-junction diode VDD–VD-PN Good Same Yes
MOS diode VDD–Vt Good Same Yes
(a)
(b)
Fig. 6.1. Schematic cross sections of (a) the p+/n-well diode, and (b) the diode-connected NMOS, in grounded p-type substrate.
Fig. 6.2. Schematic cross section of the polysilicon diode in the bulk CMOS process.
Fig. 6.3. Measured I-V curves of the polysilicon diodes with different lengths (Lc) of the un-doped region.
Fig. 6.4. Measured cut-in voltages of the polysilicon diodes with different lengths (Lc) of the un-doped region. The cut-in voltages are defined at the 1-µA forward biased current.
Fig. 6.5. Measured reverse breakdown voltages (@ 1-µA reverse biased current) and the reverse leakage currents (@ 2.5-V reverse biased voltage) of the polysilicon diodes with different lengths of un-doped region.
Fig. 6. 4-stage charge pump circuit realized with 5 polysilicon diodes.
Fig. 6.7. Photograph of the 4-stage charge pump circuit with 5 polysilicon diodes (Lc=0.5 µm) fabricated in a 0.25-µm 2.5-V bulk CMOS process.
Fig. 6.8. Measured waveforms (CLK and Vout) of the 12-stage charge pump circuit with the polysilicon diodes (Lc=0.5 µm) to drive capacitive output load. The clock frequency is 1 MHz and VDD is 2.5 V.
Fig. 6.9. Measured output voltages of the 4-stage, 8-stage, and 12-stage charge pump circuits with the polysilicon diodes of 0.5-µm and 1-µm un-doped region to drive capacitive load.
The clock frequency is 1 MHz and VDD is 2.5 V.
Fig. 6.10. Measured output voltages of the 4-stage charge pump circuit (Lc=1 µm) with the output loading of 1 MΩ, 10 MΩ, or without the output resistor under different clock frequencies. The power supply voltage (VDD) is 2.5 V.
Fig. 6.11. Measured output voltages of the 4-stage charge pump circuits with the polysilicon diodes of 0.5-µm and 1-µm un-doped region to drive capacitive loads under different VDD.
The clock frequency is 100 kHz.
Fig. 12. Measured output voltages of the 4-stage charge pump circuits (Lc=1 µm) with the output resistors of 1 MΩ and 10 MΩ and without the output resistor under different VDD.
The clock frequency is 100 kHz.
CHAPTER 7
Conclusions and Future Works
This chapter summarizes the main results of this dissertation. Then, some suggestions for the future works about the high-voltage circuit design in low-voltage CMOS processes are also addressed in this chapter.
7.1. Main Results of This Dissertation
As the semiconductor process is scaled down, the thickness of gate oxide becomes thinner in order to increase the current density of device. Besides, due to the reliability issue, the power supply voltage (VDD) must be decreased in the advanced processes. However, in an electronic system, some chips are operating at different voltage levels. Thus, some circuits must be designed in low-voltage processes but still operated at high-voltage environments. In this dissertation, several circuits operating in high-voltage environments but realized with low-voltage devices have been presented.
Chapter 2 has presented a new mixed-voltage I/O buffer realized with only thin gate-oxide (low-voltage) devices. The proposed mixed-voltage I/O buffer with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25-µm 2.5-V CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications has also been presented in Chapter 2. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers have been compared and discussed. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices can be easily applied in any 1×VDD/2×VDD mixed-voltage interface.
Chapter 3 has presented an input buffer and an output buffer realized with 1/2.5-V low-voltage devices for 3.3-V applications. Due to the high-integration trend of SOC (system-on-a-chip), an electronic system may be integrated into a single chip. Therefore, there are digital circuits and analog circuits in a chip. For example, the digital part of a chip is
designed with 1-V devices to decrease its power consumption, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. Thus, the traditional I/O circuits are not suitable for this application. An input buffer with the proposed Schmitt trigger circuit in a 0.13-µm 1/2.5-V CMOS process has been presented first. Then, an output buffer with the proposed level converter in a 0.13-µm 1/2.5-V CMOS process has been also presented in this chapter.
An NMOS-blocking technique for mixed-voltage I/O buffer design has been presented in Chapter 4. Unlike the traditional mixed-voltage I/O buffer design, the mixed-voltage I/O buffer realized with only 1×VDD devices by using the NMOS-blocking technique can receive 2×VDD, 3×VDD, and even 4×VDD input signal without the gate-oxide reliability issue. In this chapter, the 2×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation of the NMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.
Chapter 5 has presented a new charge pump circuit without the gate-oxide overstress.
Because the charge transfer switches of the new proposed charge pump circuit can be fully turned on and turned off, as well as the output stage doesn’t have the threshold drop problem, its pumping efficiency is higher than that of the prior designs. The gate-drain and the gate-source voltages of all devices in the proposed charge pump circuit don’t exceed VDD, so the proposed charge pump circuit doesn’t suffer the gate-oxide reliability problem. Besides, the proposed charge pump circuit has two pumping branches pumping the output node alternately so the output voltage ripple is small. In this work, two test chips have been implemented in a 0.35-µm 3.3-V CMOS process to verify the proposed charge pump circuit.
The measured output voltage of the new proposed 4-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD=3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed charge pump circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.
An on-chip ultra-high-voltage charge pump circuit designed with the polysilicon diodes
in low-voltage standard CMOS processes has been presented in Chapter 6. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard (bulk) CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-µm 2.5-V standard CMOS process. The measured output voltage of the 4-stage charge pump circuit with 2.5-V power supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in the 0.25-µm 2.5-V standard CMOS process.
7.2. Future Works
In this dissertation, five I/O circuits realized with low-voltage devices for high-voltage applications have been presented. However, the traditional electrostatic discharge (ESD) protection circuits are not suitable for these applications. In addition, the more robust ESD protection circuits are required in the nanometer processes. Therefore, new ESD protection circuits realized in low-voltage processes must be developed in the future.
Although the DC overstress on the gate oxide is more harmful than AC overstress, the operation frequency becomes higher in the advanced ICs. The AC overstress is also an important issue when the operation frequency is high. Thus, not only the DC overstress on the gate oxide but also the AC overstress must be considered in the high-voltage circuits realized with low-voltage devices in the future IC design.
Due to the trends of SOC and CMOS technology, more circuits will be deigned with low-voltage processes and integrated in a single chip. Thus, not only the I/O circuits and charge pump circuits but also other circuits, such as OPAMP (operational amplifier), ADC (analog-to-digital converter), and so on, must be designed in low-voltage CMOS processes for high-voltage applications. Such design topic still continues to the future research.
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