New Mixed-Voltage I/O Buffer 1

2.3.1. Circuit Implementation

Fig. 2.9 shows the new proposed mixed-voltage I/O buffer with the new dynamic n-well bias circuit and gate-tracking circuit. The new proposed I/O buffer is realized by only the thin gate-oxide devices, and occupies smaller silicon area than the prior designs of mixed-voltage I/O buffers. When the tri-state control signal OE is at 2.5 V (logic “1”), the new

mixed-voltage I/O buffer is operated in the transmit mode. The signal at the I/O pad rises or falls according to signal Dout, which is controlled by the internal circuits of IC. The lower output port of the pre-driver circuit is directly connected to the gate terminal of the pull-down NMOS device, MN1. The upper output port of the pre-driver circuit is connected to the gate terminal of the pull-up PMOS device, MP0, through the gate-tracking circuit. If the voltage level at the upper port is 0 V, the signal can be fully transmitted to the gate terminal of the pull-up PMOS device MP0 through transistor MN2, and the signal at the I/O pad is pulled up to 2.5 V. Besides, transistor MP4 is also turned on to bias the floating n-well at 2.5 V. When the voltage level at the upper port is 2.5 V, the gate terminal of transistor MP0 is charged to VDD–|Vtp| through transistor MN2 first. Consequently, the voltage at the I/O pad and the gate voltage of transistor MP1 are discharged to 0 V through transistors MN0 and MN1.

Transistor MP1 is turned on until the gate terminal of transistor MP2 is discharged to |Vtp|. At this moment, transistor MP2 is turned on to continually pull the gate voltage of transistor MP0 up to 2.5 V. The pull-up PMOS device MP0 can be completely kept off. The floating n-well is also biased at ~2.5 V through the parasitic pn-junction diodes of transistors MP0 and MP4 at this moment.

When the proposed I/O buffer is operated in the tri-state input (receive) mode, the upper and lower output ports of the pre-driver circuit are kept at 2.5 V and 0 V, respectively, to turn off transistors MP0 and MN1. Signal Din rises or falls according to the signal at the I/O pad in the tri-state input mode. In order to prevent the undesired leakage current from the I/O pad to the power supply (VDD) through the pull-up PMOS device MP0, transistor MP3 is used to track the signal at the I/O pad and to control the gate voltage of transistor MP0. When the voltage level at the I/O pad exceeds VDD+|Vtp|, such as 5 V, transistor MP3 is turned on to charge the gate terminal of transistor MP0 up to 5 V. Transistor MP0 is completely turned off to prevent the leakage current through its channel. Transistor MP4 is also turned off and the floating n-well is biased at 5 V through the parasitic pn-junction diode. Thus, there is no leakage current path from the I/O pad to the power supply (VDD). Besides, transistor MP1 is also turned on to keep transistor MP2 off in order to prevent another leakage path from the gate terminal of transistor MP0 to the upper port of the pre-driver, when the signal at the I/O pad is 5 V.

Transistors MN0 and MP5 with inverter INV are used to transfer the input signal from the I/O pad to the internal node Din in the tri-state input mode. Transistor MN0 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV. Because the gate terminal of transistor MN0 is connected to the power supply voltage (2.5 V), the input

voltage of inverter INV is limited to 1.9 V (2.5–0.6=1.9) when the voltage level at the I/O pad is 5 V. Then, transistor MP5 will pull the input node of inverter INV up to 2.5 V when the output node of inverter INV is pulled down to 0 V. The signal at the I/O pad can be successfully transferred to the internal input node Din. This I/O buffer can be correctly operated with neither gate-oxide reliability problem nor any circuit leakage issue in the tri-state input mode.

2.3.2. Simulation and Experimental Results

A 0.25-µm 2.5-V CMOS device model is used to verify the design of the new proposed mixed-voltage I/O buffer by HSPICE simulation. Figs. 2.10(a) and 2.10(b) show the simulated waveforms of the new proposed mixed-voltage I/O buffer with a 20-pF output load at the pad and 50-MHz I/O signal in the transmit mode and in the tri-state input mode, respectively. As shown in Fig. 2.10(a), the new proposed mixed-voltage I/O buffer can successfully drives the I/O pad according to signal Dout in the transmit mode. As shown in Fig. 2.10(b), the new proposed mixed-voltage I/O buffer can successfully transfer the signal at the I/O pad to the signal Din when it receives the 5-V signals in the tri-state input mode.

This simulation also verifies that the gate-drain voltages (Vgd) and gate-source voltages (Vgs) of all devices in the new proposed mixed-voltage I/O buffer do not exceed 2.5 V. Fig. 2.10(b) only shows the gate-drain voltage (Vgd) of the pull-up PMOS device MP0. With the new gate-tracking circuit, the Vgd of the pull-up PMOS device MP0 is always controlled within the normal operation voltage (VDD). Thus, the gate-tracking circuit can solve the gate-oxide reliability problem in the new proposed mixed-voltage I/O buffer.

Fig. 2.11 shows the die photograph of the new proposed mixed-voltage I/O buffer fabricated in a 0.25-µm 2.5-V 1P5M CMOS process. The measured waveforms of the new proposed mixed-voltage I/O buffer with 1-MHz I/O signal in the transmit mode, the tri-state input mode with 2.5-V input, and the tri-state input mode with 5-V input are shown in Figs.

2.12(a), 2.12(b), and 2.12(c), respectively. As shown in Figs. 2.12(a), 2.12(b), 2.12(c), the new proposed mixed-voltage I/O buffer can be successfully operated in such a 2.5/5-V mixed-voltage I/O environment. The maximum operation frequency of the proposed I/O buffer depends on the output load and the device size of output circuit. Typically, the proposed mixed-voltage I/O buffer in this work has been successfully verified in silicon that can be operated up to 200 MHz with 20-pF load.