Overview on the Prior Designs of Mixed-Voltage I/O Buffers

2.2.1. Design Concept of Mixed-Voltage I/O Buffers With Thin-Oxide Devices

Fig. 2.3 shows the mixed-voltage I/O buffer realized with thin-oxide devices, a dynamic n-well bias circuit, and a gate-tracking circuit. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. In a 0.25-µm CMOS process, the power supply voltage (VDD) is 2.5 V and the threshold voltage of the devices is about 0.6 V. Because the gate terminal of transistor MN0 is connected to 2.5 V (VDD), the drain voltage of transistor MN1 is about 1.9 V (2.5–0.6=1.9) when the input signal at the I/O pad is 5 V in the tri-state input mode. Hence, the gate-drain voltages and the gate-source voltages of the stacked NMOS devices, MN0 and MN1, are limited below 2.5 V even if the input signal at the I/O pad is 5 V. Therefore, the stacked NMOS devices, MN0 and MN1, can solve the gate-oxide reliability problem.

The gate-tracking circuit shown in Fig. 2.3 is used to prevent the leakage current path due to the incorrect conduction of the pull-up PMOS device when the input signal at the I/O pad is higher than VDD. In the transmit mode, the gate-tracking circuit must transfer the signal from the pre-driver circuit to the gate terminal of the pull-up PMOS device exactly. In the tri-state input mode (receive mode) with 5-V input signal, the gate-tracking circuit will charge the gate terminal of the pull-up PMOS device to 5 V to turn off the pull-up PMOS device completely, and to avoid the leakage current from the I/O pad to the power supply (VDD). On the contrary, the gate-tracking circuit will keep the gate terminal of the pull-up PMOS device at 2.5 V to turn off the pull-up PMOS device completely, and to prevent the overstress on the gate oxide of the pull-up PMOS device, when the input signal at the I/O pad is 0 V in the tri-state input mode.

The dynamic n-well bias circuit shown in Fig. 2.3 is designed to prevent the leakage current path due to the parasitic drain-to-well pn-junction diode in the pull-up PMOS device.

In the transmit mode, the dynamic n-well bias circuit must keep the floating n-well bias at 2.5 V. So, the threshold voltage of the pull-up PMOS device isn’t increased by the body effect. In the tri-state input mode with a 5-V input signal, the dynamic n-well bias circuit will charge the floating n-well to 5 V to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. When the input signal at the I/O pad is 0 V, the dynamic n-well bias circuit will bias the floating n-well at 2.5 V.

Because the floating n-well is clamped to 2.5 V or 5 V through the parasitic diodes by some dynamic n-well bias circuits [24], [33], [34], the voltage on the floating n-well will be a little lower than 2.5 V or 5 V. The lower floating n-well voltage results in the lower threshold voltage of the pull-up PMOS transistor. Thus, the subthreshold leakage current becomes large when the pull-up PMOS transistor is in off state. If the given process has serious subthreshold leakage issue, such as the 0.13-μm or below processes, the dynamic n-well bias circuit must clamp the floating n-well directly to the desired voltage level by the MOS transistor to decrease the subthreshold leakage.

As shown in Fig. 2.3, the extra transistors, MN2 and MP1, are added in the input buffer.

Transistor MN2 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV. Because the gate terminal of transistor MN2 is connected to the power supply voltage (VDD), the input terminal of inverter INV will rise up to 1.9 V (2.5–0.6=1.9) when the input signal at the I/O pad is 5 V in the tri-state input mode. Then, transistor MP1 is used to pull up the input node of inverter INV to 2.5 V when the output node of inverter INV is pulled down to 0 V. Thus, the gate-oxide reliability occurring in the input buffer can be solved.

2.2.2. Prior Designs of Mixed-Voltage I/O Buffers

Fig. 2.4 re-draws the mixed-voltage I/O buffer with stacked pull-up PMOS devices reported in [33]. Signal OE is the output-enable control signal. In the transmit mode, transistor MN1 is turned on and transistor MP2 is turned off, so that this I/O buffer drives the I/O pad according to the output signal Dout. In the tri-state input mode, transistor MN1 is turned off and transistor MP2 is turned on by the control signal OE at logic zero. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP1 and the floating n-well are

pulled up to 5 V through transistor MP2 and the parasitic drain-to-well pn-junction diode in transistor MP0 to prevent the undesired leakage current paths from I/O pad to power supply voltage (VDD), respectively. Although this I/O buffer is simple, transistors MN0, MN1, and MP2 have the gate-oxide reliability problem in the tri-state input mode when the input signal has a 5-V voltage level. Besides, because the stacked PMOS devices with the floating n-well to prevent the leakage current is applied to this I/O buffer, the PMOS devices in stacked configuration occupy more silicon area.

Fig. 2.5 re-draws another mixed-voltage I/O buffer with stacked pull-up PMOS devices and stacked pull-down NMOS devices [34]. This I/O buffer uses transistors MP2, MN3, and MN4 as the gate-tracking circuit and transistors MP0, MP3, and MP4 as the dynamic n-well bias circuit. In the tri-state input mode with the control signal OE at GND, transistor MN4 is turned off and transistor MP2 is turned on. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP3 is biased at 5 V through transistors MP0 and MP2 to avoid the undesired leakage current path due to the incorrect conduction of transistor MP3. The floating n-well is biased at ~5 V through the parasitic drain-to-well pn-junction diode of transistor MP0. In the transmit mode with the OE control signal at VDD, transistor MN4 is turned on so that transistor MP3 is turned on, and transistor MP2 is kept off. Hence, this I/O buffer drives the I/O pad according to the output signal Dout. When the signal at the I/O pad is 0 V, the floating n-well is biased at 2.5 V through transistor MP4. When the input signal at the I/O pad is 2.5 V, the floating n-well is biased at ~2.5 V through the parasitic source-to-well pn-junction diodes of transistors MP3 and MP4. However, transistor MP2 has the gate-oxide reliability problem when the input signal at the I/O pad is 5 V in the tri-state mode. Besides, because the I/O buffer uses two PMOS devices, MP0 and MP3, in stacked configuration to drive the I/O pad, the stacked devices occupy more silicon area.

The mixed-voltage I/O buffer with a depletion PMOS device is re-drawn in Fig. 2.6 [23].

The depletion PMOS device MP2 in the I/O buffer is used as the gate-tracking circuit. In the tri-state mode, if the input signal at I/O pad is 5 V, the gate voltage of transistor MP0 is biased at 5 V through the depletion PMOS device MP2 to avoid the undesired leakage current path through the transistor MP0. This I/O buffer uses an extra pad that is connected to 5-V power supply (VDDH) to avoid the undesired leakage current path through the parasitic drain-to-well pn-junction diode. However, using the depletion device increases mask layer and process modification. Thus, the fabrication cost of such I/O buffer design will be increased. In addition, using the extra n-well bias (VDDH) not only degrades the driving capacity of output device MP0 due to the body effect, but also increases the system cost.

Fig. 2.7 re-draws the mixed-voltage I/O buffer realized with only thin-oxide devices reported in [24]. In Fig. 2.7, the gate-tracking circuit and the dynamic n-well bias circuit are formed by transistors MP1, MP2, MP3, MP4, MN2, MN3, MN4, and MN5. In the transmit mode with signal OE at logic “1”, transistor MN4 is turned on to keep transistors MP3 and MP4 on. Thus, this I/O buffer drives the I/O pad according to signal Dout. Besides, because transistor MP3 is turned on, the floating n-well is biased at 2.5 V by transistor MP3 in the transmit mode. In the tri-state input mode with signal OE at logic “0”, transistor MN4 is kept off. If the input signal at the I/O pad is 5 V, the gate voltages of transistors MP0 and MP4 are biased at 5 V through transistor MP1 and MP2 to avoid the undesired leakage paths through the transistors MP0 and MP4. Besides, the floating n-well is also biased at ~5 V to avoid the undesired leakage path through the parasitic drain-to-well pn-junction diode of transistor MP0 when the voltage at the I/O pad is 5 V in tri-state input mode. When the input signal at the I/O pad is 0 V in the tri-state input mode, transistor MN3 is turned on to keep transistor MP3 on. So, the floating n-well is biased at 2.5 V.

Another mixed-voltage I/O buffer realized with only thin-oxide devices is re-drawn in Fig. 2.8 [25]. The gate-tracking circuit in Fig. 2.8 is composed of transistors MN3, MN4, MP2, MP3, and MP4. The dynamic n-well bias circuit in Fig. 2.8 is formed by transistors MN5, MP5, MP6, and MP7. Besides, the body terminals of all PMOS transistors in the gate-tracking circuit and the dynamic n-well bias circuit are connected to the floating n-well.

Such I/O circuit shown in Fig. 2.8 can overcome the gate-oxide reliability problem and avoid the undesired leakage paths. However, too many devices are used to realize the desired functions of the gate-tracking circuit and the dynamic n-well bias circuit. More devices used in the mixed-voltage I/O buffer often cause more complex metal routing connection in the I/O cells.