Conclusion

In this chapter, an input buffer and an output buffer realized with 1/2.5-V low-voltage devices without gate-oxide reliability issue for 3.3-V applications are presented. Besides, a Schmitt trigger circuit for the input buffer and a level converter for output buffer are also presented in this chapter. The proposed input buffer and output buffer have been fabricated in a 0.13-μm 1/2.5-V CMOS process for 3.3-V application. The experimental results show that the proposed circuits can be operated in 133-MHz 3.3-V environment correctly.

TABLE 3.1

Simulation Results of the Proposed Output Buffer Rising Delay Time (Td-rising) 1.15 ns Falling Delay Time (Td-falling) 1.08 ns

Rising Time (Trising) 0.85 ns Falling Time (Tfalling) 0.73 ns Output Low Current (IOL) 59.3 mA Output High Current (IOH) 39.4 mA

Power Consumption 29.77 mW

Fig. 3.1. Conventional input buffer in mixed-voltage interface.

(a)

(b)

Fig. 3.2. (a) Circuit and (b) transfer curve of the conventional Schmitt trigger.

(a)

(b)

Fig. 3.3. (a) Schmitt trigger with controllable hysteresis [42] and (b) two-layer Schmitt trigger [43].

Fig. 3.4. New proposed Schmitt trigger (N6 is a native NMOS transistor).

Fig. 3.5. Simulated waveforms at the nodes IN and B to compare the pull-down speed on the node B, when the transistor N6 is implemented by a native Vt device or a normal Vt device.

Fig. 3.6. Simulated waveforms at the nodes IN, OUT, A, and B of the new proposed Schmitt trigger circuit operating at 133 MHz.

Fig. 3.7. Simulated transfer curve of the new proposed Schmitt trigger circuit.

Fig. 3.8. Whole input buffer with the proposed Schmitt trigger circuit and the level-down converter.

Fig. 3.9. Layout of the new proposed Schmitt trigger circuit in the 0.13-μm 1/2.5-V CMOS process.

Fig. 3.10. Measured waveforms on nodes IN and OUT of the new proposed Schmitt trigger circuit.

Fig. 3.11. Measured transition threshold voltages VL and VH of the new proposed Schmitt trigger circuit.

Fig. 3.12. Measured transfer curve of the new proposed Schmitt trigger circuit.

Fig. 3.13. Measured waveforms on node IN and OUT of the whole input buffer shown in Fig.

3.8.

Fig. 3.14. Conventional tri-state output buffer co-designed with thin- and thick-oxide devices.

Fig. 3.15. Conventional level converter co-designed with thin-oxide and thick-oxide devices.

Fig. 3.16. The new proposed output stages realized in a 0.13-μm 1/2.5-V CMOS process (a) with all 2.5-V normal-Vt transistors, and (b) with 2.5-V native-Vt transistor N2 and 1-V normal-Vt transistor N1.

Fig. 3.17. Simulated waveforms of the output stages.

Fig. 3.18. Proposed level converter which can convert the 0/1-V signal swing to 1/3.3-V signal swing.

Fig. 3.19. Simulated waveforms of the new proposed level converter with or without transistors N3A and N3B.

Fig. 3.20. Whole output buffer which drives 3.3-V output signal in the 0.13-µm CMOS process with only 1-V and 2.5-V devices.

Fig. 3.21. Circuit implementation to realize the (a) tri-state control circuit, (b) INV1, and (c) INV2 in the whole output buffer.

Fig. 3.22. Simulated waveforms of the proposed output buffer operating with a 133-MHz 3.3-V output signal in a 0.13-µm CMOS process with only 1-V and 2.5-V devices.

Fig. 3.23. Layout of the whole output buffer in a 0.13-µm 1/2.5-V CMOS process with Cu interconnects.

Fig. 3.24. Measured waveforms of the new proposed level converter, which convert the 0/1-V signal to a 1/3.3-V signal.

Fig. 3.25. Measured waveforms of the proposed whole output buffer operating with a 133-MHz 3.3-V output signal in a 0.13-µm CMOS process with only 1-V and 2.5-V devices.

CHAPTER 4

NMOS-Blocking Technique for Mixed-Voltage I/O Buffer Design

An NMOS-blocking technique for mixed-voltage I/O buffer realized with only 1×VDD devices can receive 2×VDD, 3×VDD, and even 4×VDD input signal without the gate-oxide reliability issue is presented in this paper. The 2×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been fabricated and verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been fabricated and verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation of the NMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.

4.1. NMOS-Blocking Technique

4.1.1. Background

Several mixed-voltage I/O buffers realized with the low-voltage (thin-oxide) devices have been reported to save the wafer fabrication cost [24]-[26]. Fig. 4.1 depicts the design concept of the traditional mixed-voltage I/O buffer realized with only low-voltage devices [24]-[26]. As shown in Fig. 4.1, the stacked NMOS devices, MN0 and MN1, are used to overcome the high-voltage overstress on their gate oxide. Because the gate terminal of the transistor MN0 is connected to VDD, the maximum drain voltage of the transistor MN1 is about VDD−Vt, where Vt is the threshold voltage of NMOS. Hence, the gate-drain voltages and the gate-source voltages of the stacked devices, MN0 and MN1, are limited below VDD even if the input signal on the I/O pad is 2×VDD in the receive mode. The dynamic n-well bias circuit and the gate-tracking circuit in Fig. 4.1 are designed to prevent the leakage

current path through the parasitic drain-to-well pn-junction diode in the pull-up PMOS device and the leakage current path due to the incorrect conduction of the pull-up PMOS device, respectively. In the transmit mode, the dynamic n-well bias circuit has to keep the floating n-well at VDD. So, the threshold voltage of the pull-up PMOS device isn’t increased due to the body effect. In the transmit mode, the dynamic gate-tracking circuit should pass the output signal from the upper port of the pre-driver to the gate terminal of the pull-up PMOS device. In the receive mode with a 2×VDD input signal, the dynamic n-well bias circuit will charge the floating n-well to 2×VDD to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. When the input signal at the I/O pad is GND, the dynamic n-well bias circuit will keep the floating n-well at VDD. In the receive mode, the gate voltage of the pull-up PMOS device is controlled at VDD or 2×VDD according to the input signal on the I/O pad in order to prevent the leakage current path from the I/O pad to the power supply (VDD) through the pull-up PMOS. As shown in Fig. 4.1, the extra transistors, MN2 and MP1, are added in the input buffer. Transistor MN2 is used to limit the voltage level of the input signal reaching to the gate oxide of the inverter INV.

Because the gate terminal of transistor MN2 is connected to VDD, the input node of the inverter INV will rise up to VDD−Vt when the input signal at the I/O pad is 2×VDD in the tri-state input mode. Then, the transistor MP1 is used to pull up the input node of inverter INV to VDD when the output node of the inverter INV is pulled down to GND. Therefore, the gate-oxide reliability problem occurring in the input buffer can be solved.

Realized with the low-voltage devices, the prior mixed-voltage I/O buffers [24]-[26]

only can receive 2×VDD input signals without suffering the gate-oxide overstress. In this chapter, the NMOS-blocking technique is presented to design the mixed-voltage I/O buffers.

By using the proposed NMOS-blocking technique, not only the 2×VDD input tolerant mixed-voltage I/O buffer but also the 3×VDD and even 4×VDD input tolerant mixed-voltage I/O buffers can be achieved [53], [54]. The 2×VDD and 3×VDD input tolerant mixed-voltage I/O buffers designed with the proposed NMOS-blocking technique have been successfully verified in a 0.25-μm 2.5-V CMOS process to serve the 2.5/5-V mixed-voltage interface and in a 0.13-μm 1-V CMOS process with Cu interconnects to serve the 1/3-V mixed-voltage interface, respectively. The proposed NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation of the NMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.

4.1.2. NMOS-Blocking Technique

In an NMOS transistor as shown in Fig. 4.2, if its drain voltage (Vd) is higher than its gate voltage (Vg), the source voltage (Vs) of this NMOS device will be pulled up to Vg−Vt, where Vt is the threshold voltage of the NMOS transistor. For example, when the Vg is controlled at VDD and Vd is at 2×VDD, Vs is only pulled up to VDD−Vt. Therefore, the feature of NMOS device can be applied to design the mixed-voltage I/O buffer without the gate-oxide reliability issue and the undesired leakage currents.

Fig. 4.3 depicts the design concept of the proposed NMOS-blocking technique for mixed-voltage I/O buffer. The protection devices in Fig. 4.3 are used to block from the high-voltage input signal on the I/O pad to stress the input buffer and the output buffer of the mixed-voltage I/O circuit. As the I/O buffer is in the transmit mode, the protection devices in Fig. 4.3 have to pass the signal from node 1 to the I/O pad. As the I/O buffer is in the receive mode, the protection devices not only limit the high-voltage level of the input signal but also pass the signal information from the I/O pad to node 1. The gate voltages of the protection devices must be well controlled in both the transmit mode and the receive mode. As shown in Fig. 4.3, the mixed-voltage I/O buffer can receive (n+1)×VDD input signal without gate-oxide reliability issue by using n protection devices, where n is an integer.

4.2. 2×VDD Input Tolerant Mixed-Voltage I/O Buffer

4.2.1. Circuit Implementation

Fig. 4.4 shows the proposed 2×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique [53]. In Fig. 4.4, VDDH is as high as 2×VDD, which can be generated by an on-chip charge pump circuit with 1×VDD devices or other high-voltage generators. As shown in Fig. 4.4, transistor MN1 is used to protect the conventional I/O buffer from the input high-voltage overstress. The pre-driver can generate signals PU and PD to control the output transistors, MP0 and MN0. The dynamic gate-bias circuit in Fig. 4.4 is used to control the gate voltage of the protection transistor MN1. Table 4.1 lists the operation of the dynamic gate-bias circuit in the proposed 2×VDD input tolerant mixed-voltage I/O buffer. When this I/O buffer is in the receive mode, the gate terminal (node 2) of transistor MN1 is biased at VDD by the dynamic gate-bias circuit, whereas transistors MP0 and MN0

are both turned off by the pre-driver. At this moment, if an input signal of logic low (GND) is received from the I/O pad, node 1 is discharged to GND through transistor MN1, and this input signal can be successfully transferred to the node Din of the input buffer. When a logic high (2×VDD) signal is received from the I/O pad, the gate terminal of transistor MN1 is still biased at VDD, so the voltage on node 1 is pulled up to VDD−Vt. Because the voltage on node 1 is at VDD−Vt, the signal Din is pulled down to GND. A feedback device MP1 is added to restore the voltage level on node 1 to VDD, which avoids the undesired static dc current through the inverter INV in the input buffer. In this design, transistors MN1 and MP1 with the inverter INV can convert the 2×VDD input signal to VDD signal successfully.

Therefore, transistor MN1 can protect the I/O buffer without suffering high-voltage overstress on the gate oxide.

Fig. 4.5 depicts the dynamic gate-bias circuit in the proposed 2×VDD input tolerant I/O buffer, where transistors MP2 and MP3 are designed with the cross-coupled structure. If the gate voltage of transistor MP2 (or MP3) is pulled down, this transistor is turned on and pulls up the gate voltage of the other transistor to VDDH to turn it off. For example, if the voltage on node 5 in Fig. 4.5 is lower than VDDH−Vt and the voltage on node 6 is VDDH, transistor MN2 is turned on to keep the node 5 at VDD. In Fig. 4.5, capacitors C1 and C2 are used to couple the signals from nodes 3 and 4 to nodes 5 and 6, respectively. The voltages across these capacitors, C1 and C2, are always VDD, because the voltage levels on the top and bottom plates of capacitors C1 and C2 are either VDD and GND or 2×VDD and VDD. With these capacitors, when the voltage level on node 3 is changed from VDD to GND, the voltage on node 5 is pulled down to VDD and then the voltage level on node 6 is pulled up to 2×VDD by transistor MP3. On the contrary, when the voltage level on node 4 is converted from VDD to GND, that on node 6 is pulled to VDD, and that on node 5 is pulled up to 2×VDD by transistor MP2.

Initially, the voltages on nodes 3, 4, 5, and 6 in Fig. 4.5 could be unknown. If the voltages on nodes 5 and 6 are 2×VDD and VDD, and the voltages on nodes 3 and 4 are GND and VDD, the voltages across capacitors C1 and C2 are 2×VDD and VDD, respectively, instead of both VDD. In order to overcome this initial problem, the diode strings, DS1 and DS2, are added. The turn-on voltages of the diode strings are designed to a little higher than VDD by using multiple diodes in stacked configuration. In order to prevent the leakage current path to the grounded p-type substrate, the diode-connected MOSFET or polysilicon diode [55] is suggested. With these diode strings, if the voltage on node 3 is at GND and that on node 4 is at VDD, the voltage on node 5 is clamped at the turn-on voltage, which is a little

higher than VDD, of the diode string DS1. Therefore, transistor MP3 is turned on to pull up the voltage on node 6 to 2×VDD. Thus, the voltages across capacitors C1 and C2 are both VDD.

In the proposed 2×VDD input tolerant mixed-voltage I/O buffer, the bulk of the protection device, MN1, can be coupled to GND without the gate-oxide overstress, even if the gate voltage of transistor MN1 may be as high as 2×VDD. The reason is that this protection device, MN1, is always turned on and the voltage across the gate oxide of transistor MN1 is from the gate to the conducting channel, but not from the gate to its bulk.

Thus, the gate oxides of all NMOS devices in the dynamic gate-bias circuit are also safe because these NMOS devices are turned on when their gates are pulled up to 2×VDD.

4.2.2. Simulation and Experimental Results

The proposed 2×VDD input tolerant mixed-voltage I/O buffer has been verified in a 0.25-µm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. Fig. 4.6 shows the simulated waveforms of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the receive mode to receive the input signal of 0-to-5 V. As shown in Fig. 4.6, the gate voltage (node 2) of the transistor MN1 is always kept at 2.5 V in the receive mode, and the voltage swing on node 1 is from 0 V to 2.5 V. Fig. 4.7 shows the simulated waveforms of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the transmit mode. When the voltage on node 1 is raised up to 2.5 V, the gate voltage of the transistor MN1 is also raised to

~5 V at the same time to turn on the transistor MN1. Then, the voltage on the I/O pad is pulled up to 2.5 V. When the voltage on node 1 is dropped to 0 V, the gate voltage of the transistor MN1 is kept at 2.5 V to prevent from the high-voltage overstress on the gate oxide of the protection device MN1. The voltage on the I/O pad is therefore dropped to 0 V. With the dynamic gate-bias circuit, the proposed mixed-voltage I/O buffer can successfully transfer signals in full swing to the I/O pad through the protection device MN1.

Fig. 4.8 shows the chip photograph of the proposed 2×VDD input tolerant I/O buffer fabricated in a 0.25-µm 2.5-V CMOS process. Figs. 4.9 and 4.10 show the measured voltage waveforms on the node Dout and the I/O pad of the proposed 2×VDD input tolerant I/O buffer in the receive mode and in the transmit mode, respectively. As shown in Figs. 4.9 and 4.10, the proposed 2×VDD mixed-voltage I/O buffer by using the NMOS-blocking technique can be correctly operated in the 2.5/5-V mixed-voltage interface.

4.3. 3×VDD Input Tolerant Mixed-Voltage I/O Buffer

4.3.1. Circuit Implementation

Fig. 4.11 depicts the proposed 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique [54]. VDD is the applied power supply voltage, whereas VDDH (2×VDD) can be generated by an on-chip charge pump circuit with 1×VDD devices from VDD. The output voltage of the on-chip charge pump circuit is shared by all mixed-voltage I/O circuits in the same chip. The protection devices, MN1 and MN2, controlled by the dynamic gate-bias circuit are used to avoid the high-voltage overstress on the gate oxide. The detailed operation of the dynamic gate-bias circuit is listed in Table II.

When this I/O buffer transmits a logic low (GND), the gate voltages of transistors MN1 and MN2 are controlled at VDD, so the logic low can be transmitted from node 1 to the I/O pad.

When this I/O buffer transmits a logic high (VDD), the gate voltages of transistors MN1 and MN2 are controlled at VDDH, so the logic high can be transmitted from node 1 to the I/O pad. When this I/O buffer receives a logic low (GND), the gate voltages of transistors MN1 and MN2 are biased at VDD. Thus, the logic low signal can be transmitted to node 1 from the I/O pad. When this I/O buffer receives a logic high (3×VDD), the gate voltages of transistors MN1 and MN2 are biased at VDD and VDDH, respectively. In the 3×VDD receive mode, the voltage on node 2 (node 1) is pulled up to VDDH−Vt (VDD−Vt), where Vt is the threshold voltage of transistors. Then, the signal Din is pulled down to GND to turn on transistor MP1.

Finally, the voltage on node 1 is fully restored to VDD, so the inverter INV has no dc leakage current. In this 3×VDD input tolerant mixed-voltage I/O buffer, the gate-drain, gate-source, and drain-source voltages of every transistor don’t exceed VDD. Thus, the proposed mixed-voltage I/O buffer with 1×VDD devices in Fig. 4.11 can tolerate 3×VDD input signals without the gate-oxide reliability issue.

According to Table 4.2, the dynamic gate-bias circuit in the proposed 3×VDD input tolerant mixed-voltage I/O buffer can be designed. Fig. 4.12 shows the dynamic gate-bias circuit in the proposed 3×VDD input tolerant mixed-voltage I/O buffer. In both transmit and receive modes, the signal PU has an inverting logic level of node 3. The voltage swing of signal PU is from GND to VDD, but that of node 3 is from VDD to VDDH. Thus, a GND/VDD-to-VDD/VDDH level converter followed by an inverter can be used to generate

the signal level of node 3 to control the gate of the transistor MN1. In the transmit mode, node 3 has the same signal level of node 4. Thus, nodes 3 and 4 are connected by the transistor MP4, whose gate is connected to node 2 to avoid the gate-oxide overstress. The voltage on node 5 must be biased at VDD and VDDH alternately in the transmit mode due to the gate-oxide reliability issue of the transistor MN3. When the I/O buffer transmits a logic low, the gate voltages of transistors MN1 and MN2 are kept at VDD, and transistor MP3 is

the signal level of node 3 to control the gate of the transistor MN1. In the transmit mode, node 3 has the same signal level of node 4. Thus, nodes 3 and 4 are connected by the transistor MP4, whose gate is connected to node 2 to avoid the gate-oxide overstress. The voltage on node 5 must be biased at VDD and VDDH alternately in the transmit mode due to the gate-oxide reliability issue of the transistor MN3. When the I/O buffer transmits a logic low, the gate voltages of transistors MN1 and MN2 are kept at VDD, and transistor MP3 is