Silicon Verifications

In this work, two test chips have been fabricated in a 0.35-µm 3.3-V CMOS process to verify the proposed charge pump circuit. Fig. 5.9 shows the simulated output voltages of proposed charge pump with each pumping capacitor of 2 pF, the Dickson charge pump circuit with each pumping capacitor of 4 pF, and Wu and Chang’s charge pump circuit with each pumping capacitor of 3.2 pF in the 0.35-μm 3.3-V CMOS process. As shown in Fig. 5.9, the proposed charge pump circuit has better pumping performance. The photographs of these two test chips are shown in Figs. 10(a) and 10(b), respectively. These two test chips include the proposed 4-stage charge pump circuit with each pumping capacitors of 2 pF, the proposed 2-stage charge pump circuit with each pumping capacitor of 2 pF, Wu and Chang’s 4-stage charge pump circuit with each pumping capacitor of 2 pF, Wu and Chang’s 4-stage charge pump circuit with each pumping capacitor of 3.2 pF, the Dickson 4-stage charge pump circuit with each pumping capacitor of 2 pF, the Dickson 4-stage charge pump circuit with each

pumping capacitor of 4 pF, the proposed 4-stage charge pump circuit with each pumping capacitor of 4 pF, and the proposed 3-stage charge pump circuit with each pumping capacitor of 2 pF. To drive capacitive load, the measured output voltage of the new proposed 4-stage charge pump circuit with each pumping capacitor of 2 pF is around 8.8 V under 3.3-V power supply voltage (VDD=3.3 V). Fig. 5.11 shows the measured output voltages of the 4-stage charge pump circuits with different output currents. The measured results in Fig. 5.11 is little lower than the simulated results in Fig. 5.9 because of the parasitic resistance and capacitance from the test chips, the bonding wires, and the packages. The parasitic resistance and capacitance may results in the overlapping clock signals, which will lower the pumping efficiency. However, similar to the simulation results, the proposed charge pump circuit has better pumping performance than others, as shown in Fig. 5.11. Besides, the output voltage (~9 V) of the proposed charge pump circuit is limited by the breakdown voltage of the parasitic drain-to-bulk pn-junction diode under the low output current. If the output voltage of the charge pump circuit is larger than the breakdown voltage of the pn-junction diode, the charges leak through this diode and the output voltage of the charge pump circuit is kept at the breakdown voltage. Fig. 5.12 compares the measured output voltages of the proposed 2-stage, 3-stage, and 4-stage charge pump circuits with each pumping capacitor of 2 pF under 2-V power supply (VDD=2 V), respectively. Similarly, the measured output voltage of the proposed 4-stage charge pump circuit in Fig. 5.12 is also limited by the breakdown voltage of the parasitic pn-junction diode at low output current.

5.3.3. Discussions

Gate-oxide reliability is a time-dependent issue [8], [57]. The time period during the voltage overstress on the gate oxide is accumulated to induce the oxide breakdown. Hence, the DC stress is more harmful to the gate oxide than the short AC stress (transient stress). The diode-connected MOSFET in the Dickson charge pump circuit is used to transfer charges from the present stage to the next stage. When the diode-connected MOSFET is turned off to prevent the charges flowing back to the previous stage, the voltage across the gate oxide of the diode-connected MOSFET is around 2×VDD–Vt, where Vt is the threshold voltage of the diode-connected MOSFET. The diode-connected MOSFET will suffer serious gate-oxide overstress, so the gate oxide of the diode-connected MOSFET may be damaged after operation. In Wu and Chang’s charge pump circuit, not only these diode-connected

MOSFETs but also the charge transfer switches (CTSs) and their control circuits will suffer serious high-voltage overstress on the gate oxide. In the proposed charge pump circuit, the gate-oxide reliability issue has been considered. The gate-source voltages (Vgs) and gate-drain voltages (Vgd) of devices in the proposed charge pump circuit don’t exceed VDD whenever it is in the normal operation, start-up, or turn-off states. Therefore, the proposed charge pump circuit is better for applications in low-voltage CMOS processes.

As shown in Figs. 5.11 and 5.12, the output voltage of the proposed charge pump circuit will be limited by the breakdown voltages of the parasitic pn-junctions. As the CMOS process is scaled down, the breakdown voltages of the parasitic pn-junctions become lower.

Thus, the output voltage limitation of the charge pump circuit will become more serious. In [79], the charge pump circuit is designed in the SOI (silicon-on-insulator) process without the limitation of the breakdown voltages of the pn-junctions. However, the SOI process is more expensive than the bulk CMOS process. The charge pump circuit consisting of the polysilicon diodes, which is fully compatible to the standard bulk CMOS process, may be a good candidate to implement the charge pump circuit without the limitation of the breakdown voltages of the parasitic pn-junctions in the future [80]. The charge pump circuit designed with the polysilicon diodes will be presented in Chapter 6.

5.4. Summary

A new charge pump circuit realized with only low-voltage devices without suffering the gate-oxide reliability issue has been presented. Because the charge transfer switches of the new proposed charge pump circuit can be fully turned on and turned off, as well as the output stage doesn’t have the threshold drop problem, its pumping efficiency is higher than that of the prior designs. The gate-drain and the gate-source voltages of all devices in the proposed charge pump circuit don’t exceed VDD, so the proposed charge pump circuit doesn’t suffer the gate-oxide reliability problem. Two test chips have been implemented in a 0.35-µm 3.3-V CMOS process. The experimental results have shown that the new proposed 4-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive load is around 8.8 V under 3.3-V power supply (VDD=3.3 V). With the higher pumping gain and no overstress across the gate oxide, the new proposed charge pump circuit is more suitable for applications in low-voltage CMOS integrated circuits to generate the specified high voltage.

(a)

(b)

Fig. 5.1. 4-stage (a) diode, and (b) Dickson, charge pump circuits.

(a)

(b)

Fig. 5.2. (a) Circuit, and (b) Corresponding voltage waveforms, of the 4-stage Wu and Chang’s charge pump circuit.

(a)

(b)

Fig. 5.3. (a) Circuit, and (b) Corresponding waveforms, of the new proposed charge pump circuit with 4 pumping stages.

Fig. 5.4. Simulated waveforms on CLK, CLKB, nodes 1-8, and Vout in the new proposed 4-stage charge pump circuit.

Fig. 5.5. Simulated output voltages of the new proposed 4-stage charge pump circuit under different output currents and power supply voltages (VDD).

Fig. 5.6. Simulated output voltages of the Dickson, Wu and Chang’s, and the proposed charge pump circuits with 4 stages under different output currents with 1.8-V power supply (VDD=1.8 V).

Fig. 5.7. Simulated output voltages of the Dickson, Wu and Chang’s, and the proposed charge pump circuits with 4 stages under different VDD without output current loading.

Fig. 5.8. Simulated output waveforms of the Dickson, Wu and Chang’s, and the proposed charge pump circuits of 4 stages with 20-µA output current and 1.8-V power supply (VDD=1.8 V).

Fig. 5.9. Simulated output voltages of different 4-stage charge pump circuits in the 0.35-µm 3.3-V CMOS process under different output currents with the power supply voltage (VDD) of 3.3 V.

(a)

(b)

Fig. 5.10. Photographes of charge pump circuits in (a) chip 1, and (b) chip 2, fabricated in the 0.35-µm 3.3-V CMOS process.

Fig. 5.11. Measured output voltages of different charge pump circuits with 3.3-V power supply (VDD=3.3 V), where the stage number is 4.

Fig. 5.12. Measured output voltages of the new proposed 2-stage, 3-stage, and 4-stage charge pump circuits with 2-V power supply (VDD=2 V) under different output currents.

CHAPTER 6

Ultra-High-Voltage Charge Pump Circuit With Polysilicon Diodes in Low-Voltage Standard CMOS Processes

This chapter presents an on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage standard CMOS processes. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-µm 2.5-V standard CMOS process. The output voltage of the 4-stage charge pump circuit with 2.5-V power supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-µm 2.5-V bulk CMOS process.

6.1. Background

Charge pump circuits can generate the dc voltages those are higher than the normal power supply voltage (VDD) or lower than the ground voltage (GND). Charge pump circuits are usually applied to the nonvolatile memories, such as EEPROM and flash memories, to write or to erase the floating-gate devices [59]. Besides, charge pump circuits can be also used in some low-voltage designs to improve the circuit performance [81]. In the MEMS (micro electro mechanical systems) and electroluminescent display applications, the charge pump circuit must provide the output voltage higher than 15 V, even up to 60 V [79], [82]-[84]. Early, the pn-junction diodes were applied in the charge pump circuit. However, it is difficult to implement the fully independent pn-junction diodes in the common silicon substrate. The charge pump circuit realized with transistors in the diode-connected style was reported by Dickson [63]. Owing to the body effect, the pump efficiency of the Dickson charge pump circuit is degraded as the number of the stages increases. Several modified

charge pump circuits based on the Dickson charge pump circuit were reported to enhance the pumping efficiency [75], [77].

As the semiconductor process is scaled down, the normal circuit operation voltage (VDD) of the integrated circuits (ICs) is also decreased. The reliability issue must be considered to design the charge pump circuit in the deep-sub-micron CMOS processes, such as the gate-oxide overstress problem [77]. Fig. 6.1(a) shows the cross section of the p+/n-well diode in the grounded p-substrate with the shallow-trench isolation (STI). The p+/n-well diode is one kind of the pn-junction diodes in the bulk CMOS process. In Fig. 6.1(a), an undesired parasitic pn-junction exists between the n-well and the grounded p-type substrate.

If the voltage on the cathode of the p+/n-well diode is larger than the junction breakdown voltage between the n-well and the grounded p-substrate, the charges on the cathode will leak to ground through the parasitic pn-junction. Fig. 6.1(b) shows the cross section of the diode-connected NMOS, whose gate and drain are connected together, in the grounded p-substrate. In Fig. 6.1(b), an undesired pn-junction parasitizes between the n+ region (source/drain) and the grounded p-type substrate. Similarly, if the voltages on the cathode or anode of the diode-connected NMOS are larger than the junction breakdown voltage between the n+ region (source/drain) and the grounded p-type substrate, the charges on the cathode or anode will also leak to ground through the parasitic junction. Thus, whenever the p+/n-well (pn-junction) diodes or the diode-connected MOSFETs are used to design the charge pump circuit, the maximum output voltage will be limited by the breakdown voltage of the undesired junctions in the standard CMOS process. In the SOI (silicon-on-insulator) CMOS process, the devices are isolated to others by the insulator layer. Thus, the charge pump circuits realized in the SOI process can pump the output voltage higher without the limitation of the parasitic pn-junctions [79], [82]. However, the SOI CMOS process is more expensive than the standard (bulk) CMOS process.

In this chapter, an on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes is proposed. The polysilicon diodes have been used in the negative charge pump circuit [55] and the on-chip ESD protection circuit [85]. Because the anode and the cathode of the polysilicon diodes are fully isolated from the silicon substrate, the voltages on the anode or the cathode of the polysilicon diodes are not limited by the breakdown voltage of the undesired parasitic pn-junction. The proposed on-chip ultra-high-voltage charge pump circuit with the polysilicon diodes has been successfully implemented and verified in a 0.25-μm 2.5-V standard (bulk) CMOS process.

6.2. Polysilicon Diodes

6.2.1. Device Structure of the Polysilicon Diode

The gates of PMOS and NMOS are both realized with the n-type doped polysilicon in the early standard CMOS processes. Due to the work function consideration, the gate of PMOS and the gate of NMOS are realized with the p-type doped polysilicon and the n-type doped polysilicon, respectively, in the recent sub-quarter-micron standard CMOS processes.

In order to implement the different types of the polysilicon gates, the intrinsic polysilicon layer is deposited first, and then the p-type and n-type impurities are doped into the intrinsic polysilicon layer to form the PMOS gate and the NMOS gate, respectively. Hence, the diode can be realized on the polysilicon layer in the recent standard CMOS processes those have separated doping impurities for PMOS and NMOS gates.

Fig. 6.2 depicts the cross section of the polysilicon diode in the bulk CMOS process. As shown in Fig. 6.2, the STI layer is located above the silicon substrate. The polysilicon layer is deposited on the STI layer. Then, the p-type and n-type highly doped regions on the polysilicon are doped with the same process step of the PMOS and NMOS source/drain ion implantation, respectively. Thus, the polysilicon diode is fully compatible to the standard CMOS process without any extra process modification. Because the polysilicon diode is implemented on the STI layer, it is isolated from the silicon substrate. The charges on the anode and the cathode of the polysilicon diode don’t leak to the silicon substrate. Therefore, the polysilicon diodes can be applied to the charge pump circuit without the limitation of the parasitic junctions. In the polysilicon diode, an extra un-doped (intrinsic) polysilicon region (i) can be inserted between the p-type and n-type doped polysilicon regions. The length (Lc) of the un-doped region can be used to adjust the I-V characteristics of the polysilicon diode.

6.2.2. Characteristics of the Polysilicon Diode

The polysilicon diodes with different lengths (Lc) of the un-doped region have been fabricated in a 0.25-µm 2.5-V bulk CMOS process, where the Lc is changed from 0.25 to 1.5 µm. Fig. 6.3 shows the measured I-V curves of the polysilicon diodes with different Lc. Fig.

6.4 shows the measured cut-in voltages of the polysilicon diodes with different Lc, where the cut-in voltages are defined at the 1-µA forward biased current. In Fig. 6.4, the cut-in voltages of these polysilicon diodes vary from 0.47 to 0.58 V. As the length of the un-doped region is larger than 0.9 µm, the cut-in voltage saturates at around 0.58 V.

Fig. 6.5 shows the measured reverse breakdown voltages and the measured reverse leakage currents of the polysilicon diodes with different lengths (Lc) of the un-doped center region, where the reverse breakdown voltages are defined at the 1-µA reverse biased current and the reverse leakage currents are defined at the 2.5-V reverse biased voltage. In Fig. 6.5, the reverse breakdown voltage increases when the Lc increases. As the Lc is longer than 1.2 µm, the reverse breakdown voltage is higher than 20 V. Moreover, the reverse breakdown voltage is 33 V when the length of the un-doped region is 1.5 µm. Hence, the reverse breakdown voltage of the polysilicon diode can be adjusted by changing the length of the un-doped center region (Lc) for different applications. Besides, as shown in Fig. 6.5, because the polysilicon diodes (Lc=0.2, 0.3, 0.5, and 0.7 µm) under 2.5-V reverse biased voltage are operated at the reverse breakdown region, the reverse leakage currents of the polysilicon diodes (Lc=0.2, 0.3, 0.5, and 0.7 µm) are much larger than those of the polysilicon diodes (Lc=0.9, 1.0, 1.2, 1.3, and 1.5 µm). Because the polysilicon diodes (Lc=0.9, 1.0, 1.2, 1.3, and 1.5 µm) under 2.5-V reverse biased voltage are operated at the reverse saturation region, the leakage currents saturate lower than 1 nA.

6.3. Ultra-High-Voltage Charge Pump Circuit

6.3.1. Circuit Implementation

Fig. 6.6 depicts the 4-stage charge pump circuit designed with 5 polysilicon diodes (PD1~PD5), where the clock signals, CLK and CLKB, are out-of-phase with the amplitudes of VDD. RL and CL in Fig. 6.6 represent the output loading of resistance and capacitance, respectively. CL can make the output voltage of the charge pump circuit more stable. As shown in Fig. 6.6, the charge pump circuit uses the polysilicon diodes as the charge transfer devices. The charges are pushed from the power supply (VDD) to the output node (Vout) stage by stage every clock cycle. The voltage fluctuation between each stage can be expressed as

( )

where Vclk is the voltage amplitude of the clock signals, CLK and CLKB, Cpump is the pumping capacitance, Cpar is the parasitic capacitance at each pumping node, Io is output current, and f is the clock frequency. The output voltage of the charge pump circuit can be expressed as

Vout (VDD V ) n (= − D + ⋅ Δ −V V )_D , (6.2) where VD is the cut-in voltage of the polysilicon diode and n is the number of stages in the charge pump circuit. If Cpar and Io are small enough and Cpump is large enough, Cpar and Io can be ignored in equation 6.1. Because Vclk is usually with the same voltage level as the normal power supply voltage (VDD), the voltage fluctuation between each stage can be simply expressed as

VDD V Vclk

Δ ≈ = . (6.3) Hence, equation 6.2 can be simplified as

Vout (n 1) (VDD V )= + ⋅ − D . (6.4) The power efficiency of the charge pump circuit is defined as

Efficiency = Vout In equation 6.5, IVDD is the total current flows from the power supply (VDD). IVDD can be derived as [86]

Thus, equation 6.6 can be substituted in equation 6.5. The power efficiency of the charge pump circuit can be easily calculated.

6.3.2. Experimental Results

The 4-stage, 8-stage, and 12-stage charge pump circuits with 10-pF on-chip (MIM) pumping capacitors and the polysilicon diodes of 0.5-µm and 1-µm un-doped region have been fabricated in a 0.25-µm 2.5-V bulk CMOS process. The photograph of the 4-stage charge pump circuit realized with 5 polysilicon diodes (Lc=0.5 µm) is shown in Fig. 6.7. The independent polysilicon diodes with different lengths of the un-doped region are also implemented in this testchip.

Fig. 6.8 shows the measured waveforms of the 12-stage charge pump circuit with the polysilicon diodes (Lc=0.5 µm) to drive the capacitive output load. In Fig. 6.8, the power supply voltage (VDD) and the amplitude of the clock signals (CLK and CLKB) are 2.5 V, and the clock frequency is 1 MHz. As shown in Fig. 6.8, the output voltage of the charge pump circuit to drive the capacitive load is as high as 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in the given 0.25-µm 2.5-V bulk CMOS process.

Fig. 6.9 shows the measured output voltages of the 4-stage, 8-stage, and 12-stage charge pump circuits with the polysilicon diodes of 0.5-µm or 1-µm un-doped region (Lc). In Fig.

6.9, the proposed charge pump circuits drive only the capacitive loads with the clock frequency of 1 MHz and the power supply voltage (VDD) of 2.5 V. As shown in Fig. 6.9, the measured output voltages of the proposed charge pump circuits with the polysilicon diodes (Lc=0.5 or 1 µm) are almost the same. The length of the un-doped region (Lc) doesn’t obviously affect the output voltage of the proposed charge pump circuit because the voltage across each polysilicon diode doesn’t exceed VDD (2.5 V), which is much smaller than the reverse breakdown voltages of the polysilicon diodes (Lc=0.5 or 1 µm).

Fig. 6.10 shows the measured output voltages of the 4-stage charge pump circuit with the polysilicon diodes (Lc=1 µm) under different clock frequencies, where the power supply voltage (VDD) is 2.5 V. When the clock frequency is increased, the output voltages of the charge pump circuit are also increased. But, when the clock frequency is low, the output

Fig. 6.10 shows the measured output voltages of the 4-stage charge pump circuit with the polysilicon diodes (Lc=1 µm) under different clock frequencies, where the power supply voltage (VDD) is 2.5 V. When the clock frequency is increased, the output voltages of the charge pump circuit are also increased. But, when the clock frequency is low, the output