低電壓互補式金氧半製程下的高電壓電路設計

國 立 交 通 大 學

電子工程學系電子研究所

博 士 論 文

低電壓互補式金氧半製程下的高電壓電路設計

HIGH-VOLTAGE CIRCUIT DESIGN

IN LOW-VOLTAGE CMOS PROCESSES

研 究 生 ：陳 世 倫 (Shih-Lun Chen)

指導教授 ：柯 明 道 (Ming-Dou Ker)

低電壓互補式金氧半製程下的高電壓電路設計

HIGH-VOLTAGE CIRCUIT DESIGN

IN LOW-VOLTAGE CMOS PROCESSES

研 究 生：陳世倫

Student: Shih-Lun Chen

指導教授：柯明道

Advisor: Ming-Dou Ker

國 立 交 通 大 學

電子工程學系電子研究所

博 士 論 文

A Dissertation

Submitted to Department of Electronics Engineering

and Institute of Electronics

College of Electrical and Computer Engineering

National Chiao Tung University

in Partial Fulfillment of the Requirements

for the Degree of Doctor of Philosophy

in

Electronic Engineering

July 2006

Hsinchu, Taiwan, Republic of China

低電壓互補式金氧半製程下的高電壓電路設計

研究生：陳世倫

指導教授：柯明道 博士

國立交通大學電子工程學系電子研究所

摘要

本論文提出數個在低電壓互補式金氧半(CMOS)製程下所設計的高電

壓電路。隨著互補式金氧半製程的進步，積體電路(Integrated Circuit)的操

作速度越來越快而電晶體(Transistor)的面積越來越小。由於積體電路可靠度

(Reliability)的問題，電晶體的正常操作電壓(Normal Operation Voltage)必需

隨著製程進步而降低。另一方面，由於系統晶片(System-on-a-Chip，SOC)

的設計趨勢，單一晶片裡將包含許多不同類形的電路。所以在一個系統晶

片裡，部分電路仍然必需操作在高電壓的環境裡。如果利用低電壓製程所

設計的積體電路操作在高電壓的環境，閘極氧化層可靠度(Gate-Oxide

Reliability)、熱載子衰退效應(Hot-Carrier Degradation)、漏電流(Leakage

Current)等現象將會發生。所以本論文提出了數個低電壓互補式金氧半製程

下所設計的高電壓電路，且無閘極氧化層可靠度、熱載子衰退效應、漏電

流等問題。本論文所提出的電路適合實現在深次微米(Deep Sub-Micron

Meter)，甚至是奈米(Nano Meter)互補式金氧半製程裡。本論文共包含七個

章節。

在第二章中，本論文提出了兩個利用低電壓元件所實現的混合電壓介

面輸入輸出電路(Mixed-Voltage I/O Buffer)。這兩個混合電壓介面輸入輸出

電路擁有新型的動態 N 阱偏壓電路(Dynamic N-Well Bias Circuit)和閘極電

壓 追 蹤 電 路 (Gate-Tracking Circuit) 來 避 免 混 合 電 壓 介 面 (Mixed-Voltage

Interface)所造成的漏電流的問題。此外，這兩個混合電壓介面輸入輸出電

路也避免了閘極電壓過高所造成的閘極氧化層可靠度問題。跟先前的混合

電壓介面輸入輸出電路比較，本論文所提出的兩個利用低電壓元件所實現

的混合電壓介面輸入輸出電路擁有較小的面積。此外，本論文所提出的第

二個混合電壓介面輸入輸出電路解決了浮接 N 阱(Floating N-Well)的現象，

將可大量減少次臨介漏電流(Subthreshold Leakage Current)的問題。其更適

用於先進製程下的設計。本論文所提出的兩個利用低電壓元件所實現的混

合電壓介面輸入輸出電路已經在 2.5 伏 0.25 微米互補式金氧半製程裡實現

並驗證。

由於系統晶片的需求，單一晶片內可能包含數位電路以及類比電路。

以 1/2.5 伏 0.13 微米互補式金氧半製程來說，數位電路用 1 伏元件來實現

以減少功率消耗(Power Consumption)和矽面積(Silicon Area)，類比電路以

2.5 伏元件來實現以保持電路的效能(Performance)，但此系統晶片的介面是

3.3 伏，例如 PCI-X 的介面。因此，在第三章中，提出了應用在 3.3 伏的環

境且利用 1/2.5 伏製程所實現的輸入電路和輸出電路。此外，一個新型的史

密特觸發器(Schmitt Trigger)和電壓準位轉換器(Level Converter)分別被應用

在所提出的輸入電路和輸出電路。本論文所提出應用在 3.3 伏環境的輸入

電路和輸出電路已經在 1/2.5 伏 0.13 微米互補式金氧半製程裡實現並已在

3.3 伏的操作環境下驗證。

有別於傳統的混合電壓介面輸入輸出電路使用動態 N 阱偏壓電路和閘

極電壓追蹤電路來避免漏電流以及閘極氧化層可靠度的問題。在第四章

中，本論文提出了用 N 型金氧半場效電晶體(NMOS)阻隔的技巧來設計混

合電壓介面輸入輸出電路。使用此 N 型金氧半場效電晶體阻隔的技巧不但

能設計出接收兩倍操作電壓輸入訊號的混合電壓介面輸入輸出電路，甚至

可設計三倍、四倍、五倍操作電壓輸入訊號的混合電壓介面輸入輸出電路。

其限制在於寄生 PN 接面(PN-Junction)的崩潰電壓(Breakdown Voltage)。利

用所提出的 N 型金氧半場效電晶體阻隔的技巧所設計的接收兩倍操作電壓

輸入訊號的混合電壓介面輸入輸出電路已經在 2.5 伏 0.25 微米互補式金氧

半製程裡實現並在 2.5/5 伏的混合電壓介面下驗證。而利用所提出的 N 型

金氧半場效電晶體阻隔的技巧所設計的接收三倍操作電壓輸入訊號的混合

電壓介面輸入輸出電路已經在 1 伏 0.13 微米互補式金氧半製程裡實現並在

1/3 伏的混合電壓介面下驗證。

電荷幫浦電路(Charge Pump Circuit)是用來產生一個高於電源電壓

(Power Supply Voltage)的輸出電壓。當利用低電壓元件來設計傳統的電荷幫

浦電路時，將會發生嚴重的閘極氧化層可靠度問題。因此，在第五章中，

本論文提出了一個新型的電荷幫浦電路，其避免了閘極電壓過高所造成的

閘極氧化層可靠度問題。此外，本論文所提出的電荷幫浦電路有較好的效

能(Performance)其輸出的漣波電壓(Output Voltage Ripple)也比傳統的電荷

幫浦電路小。本論文所提出的電荷幫浦電路已經在 3.3 伏 0.35 微米互補式

金氧半製程裡實現並驗證。

在互補式金氧半製程裡實現電荷幫浦電路，其輸出電壓將會被寄生 PN

接面的崩潰電壓所限制。此外，隨著互補式金氧半製程的進步，寄生 PN

接面的崩潰電壓也隨著降低。由於系統晶片的需求，在低電壓製程裡產生

一個高電壓是必需的。因此，在第六章中，本論文提出了用多晶矽二極體

(Polysilicon Diode)所實現的電荷幫浦電路。此多晶矽二極體利用淺溝隔絕

層(Shallow Trench Isolation Layer)與基底(Substrate)相隔絕，所以流經此多

晶矽二極體的電荷不會經由寄生 PN 接面的崩潰流失到基底。換句話說，

本論文提出用多晶矽二極體所實現的電荷幫浦電路，其輸出電壓不會被寄

生 PN 接面的崩潰電壓所限制。此外，多晶矽二極體並不會增加額外的製

程步驟，其與標準的互補式金氧半製程相容(Compatible)。本論文提出用多

晶矽二極體所實現的電荷幫浦電路已經在 2.5 伏 0.25 微米標準互補式金氧

半製程裡實現並驗證。其輸電壓遠高於寄生 PN 接面的崩潰電壓。

在本博士論文中提出數個在低電壓互補式金氧半製程下所設計的高電

壓電路。所提出的電路已在實際晶片上成功驗証，並有相對應的國際會議

論文、國際期刊論文發表與專利申請。

HIGH-VOLTAGE CIRCUIT DESIGN

IN LOW-VOLTAGE CMOS PROCESSES

Student: Shih-Lun Chen Advisor: Dr. Ming-Dou Ker

Department of Electronics Engineering and Institute of Electronics

National Chiao Tung University

ABSTRACT

The scaling trend of the CMOS technology is toward the nanometer region to increase the speed and density of the transistors in integrated circuits. Due to the reliability issue, the power supply voltage is also decreased with the advanced technologies. However, in an electronic system, some circuits could be still operated at high voltage levels. If the circuits realized with low-voltage devices are operated at high voltage levels, the gate-oxide breakdown, hot-carrier degradation, leakage issues, and so on will occur. Therefore, designing the high-voltage circuits in low-voltage CMOS processes is an important topic in today and future VLSI (very large scale integration) design. In this dissertation, several circuits designed in low-voltage CMOS processes but operated in high-voltage environments are presented. There are seven chapters included in this dissertation.

Two new mixed-voltage I/O buffers realized with low-voltage devices are presented in Chapter 2 to prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. These two new mixed-voltage I/O buffer have novel gate-tracking circuits and dynamic n-well bias circuits. Compared with the prior designs of mixed-voltage I/O buffers, these two new mixed-voltage I/O buffers occupy smaller silicon area. Besides, the new proposed mixed-voltage I/O buffer 2 can be applied for high-speed applications without the gate-oxide reliability problem and the circuit leakage issue. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices

can be easily applied in 1×VDD/2×VDD mixed-voltage interface.

Due to the high-integration trend of SOC (system-on-a-chip), an electronic system may be integrated into a single chip. Hence, there are digital circuits and analog circuits integrated in a single chip. For example, the digital part of the SOC is designed with 1-V devices to decrease its power consumption, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. Thus, the traditional I/O circuits are not suitable for this application. An input buffer with the proposed Schmitt trigger circuit and an output buffer with the proposed level converter in a 0.13-µm 1/2.5-V CMOS process are presented in Chapter 3 for 3.3-V applications.

An NMOS-blocking technique for mixed-voltage I/O buffer design is presented in Chapter 4. Unlike the traditional mixed-voltage I/O buffer design, the mixed-voltage I/O buffer realized with only 1×VDD devices by using the NMOS-blocking technique can receive 2×VDD, 3×VDD, and even 4×VDD input signals without the gate-oxide reliability issue. In this dissertation, the 2×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface. The NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation of the NMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.

A new charge pump circuit without the gate-oxide overstress is presented in Chapter 5. Because the charge transfer switches of the new proposed charge pump circuit can be fully turned on and turned off, as well as the output stage doesn’t have the threshold drop problem, its pumping efficiency is higher than that of the prior designs. The gate-drain and the gate-source voltages of all devices in the new charge pump circuit don’t exceed VDD, so the new charge pump circuit doesn’t suffer the gate-oxide reliability problem. Besides, the proposed charge pump circuit has two pumping branches pumping the output node alternately so the output voltage ripple is small. The proposed circuit is suitable in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.

In general, the output voltage of the charge pump circuit will be limited by the breakdown voltage of the parasitic pn-junction in the given CMOS process. Chapter 6

presents an on-chip ultra-high-voltage charge pump circuit designed with the polysilicon diodes in low-voltage standard CMOS processes. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of parasitic pn-junction. The polysilicon diodes can be implemented in the standard (bulk) CMOS processes without extra process steps. The proposed charge pump circuit designed with the polysilicon diodes has been fabricated and verified in a 2.5-V 0.25-µm bulk CMOS process.

In summary, several circuits designed in low-voltage CMOS processes but operated in high-voltage environments are presented in this dissertation. The proposed circuits have been implemented and verified in silicon chips. The proposed circuits are very useful and cost-efficient for the advanced SOC applications.

ACKNOWLEDGEMENTS

在交通大學電子研究所的生涯中，首先要感謝我的指導教授柯明道教授

在這些年來耐心的指導與鼓勵，使我能順利完成博士學業。不只在專業領

域上的知識，從柯教授認真的研究態度和嚴謹的處事原則，也讓我學習到

克服困難、解決問題的正確態度與方法。此外，感謝 307 實驗室另外四位

師長，吳重雨教授、吳錦川教授、吳介琮教授以及陳巍仁教授給我的指導

與建議。

感謝黃弘一教授帶領我進入積體電路設計的殿堂，奠定了我在電路設計

上的基礎。還有感謝周世傑教授、馬金溝博士、鄭國興教授在百忙之中抽

空來擔任我的口試委員，給我指導跟建議，讓整個論文更加完整。

感謝廖以義博士，在我初來到交通大學時，給我許多生活、學業上的建

議與幫助。還有謝謝其他 307 實驗室的成員陳東暘博士、林子超博士、施

育全博士、周忠昀博士、徐國鈞博士、林坤賢博士，林俐如、周儒明、李

瑞梅、范啟威、王文傑、范振麟、翟芸、陳榮昇、許勝福、鄧至剛、徐新

智、蘇烜毅、虞繼堯、張瑋仁、曾偉信、顏承正、蕭淵文、李健銘、陳世

宏、陳志豪、陳煒明、王暢資、王資閔等學長姐、同學、學弟們在課業、

研究、生活上的幫忙與協助，讓我順利完成我的博士論文、並學習到做人

處事上的態度與方法。此外，感謝歷任 307 實驗室的助理李婷媛小姐、卓

慧貞小姐在實驗室行政事務上的許多協助。

致上最深的感謝給我親愛的家人們，祖母林玉雲女士、父親陳祐榮先

生、母親鄭素嬌女士、弟弟陳亞倫、妹妹陳亞雯以及其他家人們。有了您

們的支持、鼓勵、陪伴和照顧，才能讓我順利完成學業。還要謝謝女友鄭

立欣小姐，一路上陪伴著我。最後謝謝所有幫助我、陪著我成長的人。謝

謝你們。

陳 世 倫

誌於風城交大

95 年 夏

CONTENTS

Figure Captions xvii

Chapter 1. Introduction 1

1.1. Scaling Trend of CMOS Technology 1

1.1.1. Gate-Oxide Breakdown 2

1.1.2. Hot-Carrier Degradation 2

1.2. Issues of High-Voltage Circuit Design in Low-Voltage CMOS Processes 3

1.3. Organization of This Dissertation 4

Chapter 2. Mixed-Voltage I/O Buffers With Only Thin Gate-Oxide Devices 11

2.1. Issues of Mixed-Voltage I/O Interface 11

2.2. Overview on the Prior Designs of Mixed-Voltage I/O Buffers 13

2.2.1. Deign Concepts of Mixed-Voltage I/O Buffers With Thin-Oxide Devices 13

2.2.2. Prior Designs of Mixed-Voltage I/O Buffers 14

2.3. New Mixed-Voltage I/O Buffer 1 16

2.3.1. Circuit Implementation 16

2.3.2. Simulation and Experimental Results 18

2.4. New Mixed-Voltage I/O Buffer 2 19

2.4.1. Circuit Implementation 19

2.4.2. Simulation Results 19

2.5. Discussions and Comparisons 20

2.5.1. Speed 20

2.5.2. Power Consumption 20

2.5.3. Area 21

2.5.4. Noise, Latch-Up, and Subthreshold Leakage Issues 22

2.5.6. Comparisons 22

2.6. Summary 23

Chapter 3. 3.3-V Input Buffer and Output Buffer in 0.13-μm 1/2.5-V CMOS Process 39

3.1. Input Buffer 39

3.1.1. Background 39

3.1.2. Schmitt Trigger Design 41

3.1.3. Whole Input Buffer Design 43

3.1.4. Experimental Results 43

3.1.5. Summary 44

3.2. Output Buffer 44

3.2.1. Background 44

3.2.2. Output Stage Design 46

3.2.3. Level Converter Design 47

3.2.4. Whole Output Buffer Design 48

3.2.5. Experimental Results 49

3.2.6. Discussions 49

3.2.7. Summary 50

3.3. Conclusion 50

Chapter 4. NMOS-Blocking Technique for Mixed-Voltage I/O Buffer Design 65

4.1. NMOS-Blocking Technique 65

4.1.1. Background 65

4.1.2. NMOS-Blocking Technique 67

4.2. 2×VDD Input Tolerant Mixed-Voltage I/O Buffer 67

4.2.1. Circuit Implementation 67

4.2.2. Simulation and Experimental Results 69

4.3. 3×VDD Input Tolerant Mixed-Voltage I/O Buffer 70

4.3.1. Circuit Implementation 70

4.3.2. Simulation and Experimental Results 71

4.4. Discussions 72

4.4.1. Limitation of the NMOS-Blocking Technique 72

4.4.2. Gate-Oxide Overstress 73

4.4.4. Speed Degradation of the NMOS-Blocking Technique 74

4.4.5. Advantages of the NMOS-Blocking Technique 74

4.4.6. Duty Cycle 74

4.5. Summary 75

Chapter 5. Charge Pump Circuit Without Gate-Oxide Reliability Issue in Low-Voltage Processes 87

5.1. Background 87

5.2. New Charge Pump Circuit Without Gate-Oxide Reliability Issue 90

5.3. Verifications and Comparisons 91

5.3.1. Simulation Results and Comparisons 91

5.3.2. Silicon Verifications 93

5.3.3. Discussions 94

5.4. Summary 95

Chapter 6. Ultra-High-Voltage Charge Pump Circuit With Polysilicon Diodes in Low-Voltage Standard CMOS Processes 105

6.1. Background 105

6.2. Polysilicon Diodes 107

6.2.1. Device Structure of the Polysilicon Diode 107

6.2.2. Characteristics of the Polysilicon Diode 107

6.3. Ultra-High-Voltage Charge Pump Circuit 108

6.3.1. Circuit Implementation 108

6.3.2. Experimental Results 109

6.3.3. Discussions 111

6.4. Summary 111

Chapter 7. Conclusions and Future Works 121

7.1. Main Results of This Dissertation 121

7.2. Future Works 123

References 125

VITA 133

TABLE CAPTIONS

Table 1.1. Key features of the semiconductor scaling trend (high-performance logic technology) [1].

Table 2.1. Comparison on delay among the mixed-voltage I/O buffers in the transmit mode.

Table 2.2. Comparison on power consumption among the mixed-voltage in the transmit mode.

Table 2.3. Comparison on area (device sizes) among the mixed-voltage I/O buffers. Table 2.4. Comparison on features among the mixed-voltage I/O buffers.

Table 3.1. Simulation results of the proposed output buffer.

Table 4.1. Operation of the dynamic gate-bias circuit in the proposed 2×VDD input tolerant mixed-voltage I/O buffer.

Table 4.2. Operation of the dynamic gate-bias circuit in the proposed 3×VDD input tolerant mixed-voltage I/O buffer.

Table 6.1. Summary of the polysilicon diode (this work), pn-junction diode, MOS diode charge pump circuits.

FIGURE CAPTIONS

Fig. 1.1. Scaling trends of the oxide thickness and the power supply voltage [1]. Fig. 1.2. A CMOS inverter realized with 2.5-V devices in 5-V environment.

Fig. 1.3. An NMOS load amplifier realized with 2.5-V devices in 5-V environment. Fig. 1.4. Two CMOS inverters realized with 2.5-V devices in 2.5/5-V mixed-voltage

interface.

Fig. 2.1. Conventional tri-state I/O buffer in a 0.25-µm CMOS process that will suffer the circuit leakage and gate-oxide reliability issue in the mixed-voltage I/O interface.

Fig. 2.2. Mixed-voltage I/O buffer with dual-oxide option and an external n-well bias. Fig. 2.3. Basic design concept for mixed-voltage I/O buffer realized with only

thin-oxide devices.

Fig. 2.4. Mixed-voltage I/O buffer with stacked pull-up PMOS devices [33].

Fig. 2.5. Mixed-voltage I/O buffer with stacked pull-up PMOS devices and stacked pull-down NMOS devices [34].

Fig. 2.6. Mixed-voltage I/O buffer with a depletion PMOS device MP2 [23]. Fig. 2.7. Mixed-voltage I/O buffer realized with only thin-oxide devices [24]. Fig. 2.8. Mixed-voltage I/O buffer realized with only thin-oxide devices [25]. Fig. 2.9. New mixed-voltage I/O buffer 1 with only thin-oxide devices.

Fig. 2.10. Simulated waveforms of the new proposed mixed-voltage I/O buffer 1 with a 20-pF load and 50-MHz I/O signal in (a) the transmit mode, and (b) the tri-state (receive) mode.

Fig. 2.11. Die photograph of the new proposed mixed-voltage I/O buffer 1 fabricated in a 0.25-µm 2.5-V CMOS process.

Fig. 2.12. Measured waveforms of the new proposed mixed-voltage I/O buffer 1 with 1-MHz I/O signal in (a) the transmit mode, (b) the tri-state input mode with 2.5-V input, and (c) the tri-state input mode with 5-V input.

Fig. 2.13. New proposed mixed-voltage I/O buffer 2 with only thin-oxide devices.

Fig. 2.14. Simulated waveforms of the new proposed mixed-voltage I/O buffer 2 with a 20-pF load and 50-MHz I/O signal in (a) the transmit mode, and (b) the tri-state input (receive) mode.

the new mixed-voltage I/O buffers 1 and 2, during the signal transition on the I/O pad. (a) In transmit mode, and (b) in receive mode.

Fig. 3.1. Conventional input buffer in mixed-voltage interface.

Fig. 3.2. (a) Circuit and (b) transfer curve of the conventional Schmitt trigger.

Fig. 3.3. (a) Schmitt trigger with controllable hysteresis [42] and (b) two-layer Schmitt trigger [43].

Fig. 3.4. New proposed Schmitt trigger (N6 is a native NMOS transistor).

Fig. 3.5. Simulated waveforms at the nodes IN and B to compare the pull-down speed on the node B, when the transistor N6 is implemented by a native Vt device or a normal Vt device.

Fig. 3.6. Simulated waveforms at the nodes IN, OUT, A, and B of the new proposed Schmitt trigger circuit operating at 133 MHz.

Fig. 3.7. Simulated transfer curve of the new proposed Schmitt trigger circuit.

Fig. 3.8. Whole input buffer with the proposed Schmitt trigger circuit and the level-down converter.

Fig. 3.9. Layout of the new proposed Schmitt trigger circuit in the 0.13-μm 1/2.5-V CMOS process.

Fig. 3.10. 3.10. Measured waveforms on nodes IN and OUT of the new proposed Schmitt trigger circuit.

Fig. 3.11. Measured transition threshold voltages VL and VH of the new proposed

Schmitt trigger circuit.

Fig. 3.12. Measured transfer curve of the new proposed Schmitt trigger circuit.

Fig. 3.13. Measured waveforms on node IN and OUT of the whole input buffer shown in Fig. 3.8.

Fig. 3.14. Conventional tri-state output buffer co-designed with thin- and thick-oxide devices.

Fig. 3.15. Conventional level converter co-designed with thin-oxide and thick-oxide devices.

Fig. 3.16. The new proposed output stages realized in a 0.13-μm 1/2.5-V CMOS process (a) with all 2.5-V normal-Vt transistors, and (b) with 2.5-V native-Vt transistor N2 and 1-V normal-Vt transistor N1.

Fig. 3.17. Simulated waveforms of the output stages.

Fig. 3.18. Proposed level converter which can convert the 0/1-V signal swing to 1/3.3-V signal swing.

Fig. 3.19. Simulated waveforms of the new proposed level converter with or without transistors N3A and N3B.

Fig. 3.20. Whole output buffer which drives 3.3-V output signal in the 0.13-µm CMOS process with only 1-V and 2.5-V devices.

Fig. 3.21. Circuit implementation to realize the (a) tri-state control circuit, (b) INV1, and (c) INV2 in the whole output buffer.

Fig. 3.22. Simulated waveforms of the proposed output buffer operating with a 133-MHz 3.3-V output signal in a 0.13-µm CMOS process with only 1-V and 2.5-V devices.

Fig. 3.23. Layout of the whole output buffer in a 0.13-µm 1/2.5-V CMOS process with Cu interconnects.

Fig. 3.24. Measured waveforms of the new proposed level converter, which convert the 0/1-V signal to a 1/3.3-V signal.

Fig. 3.25. Measured waveforms of the proposed whole output buffer operating with a 133-MHz 3.3-V output signal in a 0.13-µm CMOS process with only 1-V and 2.5-V devices.

Fig. 4.1. Mixed-voltage I/O buffer realized with only thin-oxide devices in the mixed-voltage interface.

Fig. 4.2. An NMOS transistor, whose gate and drain are biased at VDD and 2×VDD, respectively.

Fig. 4.3. Proposed NMOS-blocking technique for mixed-voltage I/O buffer.

Fig. 4.4. 2×VDD input tolerant mixed-voltage I/O buffer by using the proposed NMOS-blocking technique.

Fig. 4.5. Dynamic gate-bias circuit in the proposed 2×VDD input tolerant mixed-voltage I/O buffer.

Fig. 4.6. Simulated waveforms of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the receive mode with 5-V input signals.

Fig. 4.7. Simulated waveforms of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the transmit mode.

Fig. 4.8. Chip photograph of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in a 0.25-µm 2.5-V CMOS process.

Fig. 4.9. Measured waveforms on the node Din and I/O pad of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the receive mode with 5-V input signals.

Fig. 4.10. Measured waveforms on the node Dout and I/O pad of the proposed 2×VDD input tolerant mixed-voltage I/O buffer in the transmit mode with 2.5-V output signals.

Fig. 4.11. 3×VDD input tolerant mixed-voltage I/O buffer by using the proposed NMOS-blocking technique.

Fig. 4.12. Dynamic gate-bias circuit in the proposed 3×VDD input tolerant mixed-voltage I/O buffer.

Fig. 4.13. Simulated waveforms of the proposed 3×VDD input tolerant mixed-voltage I/O buffer in the receive mode to receive 133-MHz 3×VDD (3-V) input signals. The waveforms are shown to observe the voltages at the nodes of I/O pad, Din, node 1, node 2, node 3, and node 4 in Fig. 4.11.

Fig. 4.14. Simulated waveforms of the proposed 3×VDD input tolerant mixed-voltage I/O buffer in the transmit mode to drive 133-MHz 3×VDD (3-V) output signals. The waveforms are shown to observe the voltages at the nodes of I/O pad, Din, node 1, node 2, node 3, and node 4 in Fig. 4.11.

Fig. 4.15. Layout of the proposed 3×VDD input tolerant mixed-voltage I/O buffer in a 0.13-µm 1-V CMOS process with Cu interconnects.

Fig. 4.16. Measured voltage waveforms of the proposed 3×VDD input-tolerant mixed-voltage I/O buffer in the receive mode to successfully receive 3×VDD (3-V) input signals.

Fig. 4.17. Measured voltage waveforms of the proposed 3×VDD input-tolerant mixed-voltage I/O buffer in the transmit mode to drive 1×VDD (1-V) output signals.

Fig. 4.18. 4×VDD input tolerant mixed-voltage I/O buffer by using the proposed NMOS-blocking technique.

Fig. 4.19. Equivalent circuit of the mixed-voltage I/O buffer designed with the proposed NMOS-blocking technique.

Fig. 5.1. 4-stage (a) diode, and (b) Dickson, charge pump circuits.

Fig. 5.2. (a) Circuit, and (b) Corresponding voltage waveforms, of the 4-stage Wu and Chang’s charge pump circuit.

Fig. 5.3. (a) Circuit, and (b) Corresponding waveforms, of the new proposed charge pump circuit with 4 pumping stages.

Fig. 5.4. Simulated waveforms on CLK, CLKB, nodes 1-8, and Vout in the new proposed 4-stage charge pump circuit.

Fig. 5.5. Simulated output voltages of the new proposed 4-stage charge pump circuit under different output currents and power supply voltages (VDD).

Fig. 5.6. Simulated output voltages of the Dickson, Wu and Chang’s, and the proposed charge pump circuits with 4 stages under different output currents with 1.8-V power supply (VDD=1.8 V).

Fig. 5.7. Simulated output voltages of the Dickson, Wu and Chang’s, and the proposed charge pump circuits with 4 stages under different VDD without output current loading.

Fig. 5.8. Simulated output waveforms of the Dickson, Wu and Chang’s, and the proposed charge pump circuits of 4 stages with 20-µA output current and 1.8-V power supply (VDD=1.8 V).

Fig. 5.9. Simulated output voltages of different 4-stage charge pump circuits in the 0.35-µm 3.3-V CMOS process under different output currents with the power supply voltage (VDD) of 3.3 V.

Fig. 5.10. Photographes of charge pump circuits in (a) chip 1, and (b) chip 2, fabricated in the 0.35-µm 3.3-V CMOS process.

Fig. 5.11. Measured output voltages of different charge pump circuits with 3.3-V power supply (VDD=3.3 V), where the stage number is 4.

Fig. 5.12. Measured output voltages of the new proposed 2-stage, 3-stage, and 4-stage charge pump circuits with 2-V power supply (VDD=2 V) under different output currents.

Fig. 6.1. Schematic cross sections of (a) the p+/n-well diode, and (b) the diode-connected NMOS, in grounded p-type substrate.

Fig. 6.2. Schematic cross section of the polysilicon diode in the bulk CMOS process. Fig. 6.3. Measured I-V curves of the polysilicon diodes with different lengths (Lc) of

the un-doped region.

Fig. 6.4. Measured cut-in voltages of the polysilicon diodes with different lengths (Lc) of the un-doped region. The cut-in voltages are defined at the 1-µA forward biased current.

Fig. 6.5. Measured reverse breakdown voltages (@ 1-µA reverse biased current) and the reverse leakage currents (@ 2.5-V reverse biased voltage) of the polysilicon diodes with different lengths of un-doped region.

Fig. 6.7. Photograph of the 4-stage charge pump circuit with 5 polysilicon diodes (Lc=0.5 µm) fabricated in a 0.25-µm 2.5-V bulk CMOS process.

Fig. 6.8. Measured waveforms (CLK and Vout) of the 12-stage charge pump circuit with the polysilicon diodes (Lc=0.5 µm) to drive capacitive output load. The clock frequency is 1 MHz and VDD is 2.5 V.

Fig. 6.9. Measured output voltages of the 4-stage, 8-stage, and 12-stage charge pump circuits with the polysilicon diodes of 0.5-µm and 1-µm un-doped region to drive capacitive load. The clock frequency is 1 MHz and VDD is 2.5 V.

Fig. 6.10. Measured output voltages of the 4-stage charge pump circuit (Lc=1 µm) with the output loading of 1 MΩ, 10 MΩ, or without the output resistor under different clock frequencies. The power supply voltage (VDD) is 2.5 V.

Fig. 6.11. Measured output voltages of the 4-stage charge pump circuits with the polysilicon diodes of 0.5-µm and 1-µm un-doped region to drive capacitive loads under different VDD. The clock frequency is 100 kHz.

Fig. 6.12. Measured output voltages of the 4-stage charge pump circuits (Lc=1 µm) with the output resistors of 1 MΩ and 10 MΩ and without the output resistor under different VDD. The clock frequency is 100 kHz.

CHAPTER 1

Introduction

In this chapter, the background of this dissertation is discussed. First, the scaling trend of the CMOS technology is introduced. The reliability issue about the gate-oxide breakdown and the hot-carrier degradation in the advanced technology are also discussed. Then, the issues of the high-voltage circuits realized in low-voltage CMOS processes are discussed. Finally, the rest of this dissertation is organized.

1.1. Scaling Trend of CMOS Technology

The scaling trend of the CMOS technology is to increase the speed and density of the transistors in integrated circuits. The increase of speed requires the higher current density of the transistor due to the charge or discharge the load capacitance if the load capacitance is kept the same. Equation 1.1 expresses the drain current (Id) of the NMOS transistor in the

saturation region, where μn is the mobility of the NMOS transistor, Cox is the gate capacitance

per unit area of the NMOS transistor, W and L are the channel width and channel length of the NMOS transistor, Vt is the threshold voltage of the NMOS transistor, λ is the channel-length modulation parameter.

I_{d n} C_ox W (Vgs Vt) (12 Vds) L

μ

= ⋅ ⋅ ⋅ − ⋅ − ⋅λ (1.1) If ignoring the channel-length modulation, equation 1.1 can be simplified as equation 1.2.

2 ( d n ox W ) I C Vgs V L μ = ⋅ ⋅ ⋅ − t (1.2) Hence, the dimension and the threshold voltage of the devices are the key parameters as the semiconductor technology is scaled down. For speed consideration, the operation voltage of device is as high as possible to maximize the current density. However, the operation voltage of the device is decreased owing to the reliability issue. Table 1.1 summarizes the key features of the semiconductor scaling trend, which are predicted by the Semiconductor Industry Association (SIA) [1]. As shown in Table 1.1, the gate length (L), the threshold

voltage (Vt), and the thickness (tox) of the gate oxide are decreased in the future technologies

so the drain current is increased. However, due to the reliability issue, the power supply voltage is decreased in the future technologies. Although the scaling trend is toward to increase the speed and the density of transistor, the reliability issue becomes more responsible in the future technologies. Because the thickness of gate oxide is getting thinner and thinner, and the channel length is getting shorter and shorter in the future technologies, the gate-oxide breakdown [2]-[5] and hot-carrier degradation [6], [7] issues become more important.

1.1.1. Gate-Oxide Breakdown

The thinner gate oxide is required in the advanced processes due to the current density of the device. If the other device dimensions are scaled down and the gate oxide is kept the same, the device suffers from the short-channel effect. However, the larger electric field is across the gate oxide if the thickness of the gate oxide is scaled down and the operation voltage is not. The large electric field on the gate oxide may cause the gate-oxide breakdown. The gate oxide can be broken down instantaneously or broken down over time [8], [9]. Equation 1.3 expresses the lifetime of gate oxide over the voltage stress [8].

0 0 1 exp 1 ( ) BD t _eff ox G X dt V t τ ⋅ ⎛ ⎞ − ⋅ = ⎜ ⎟ ⎝ ⎠

∫

due to the defeats, and Vox(t) is the time-dependent voltage across the gate oxide. As

expressed in equation 1.3, the accumulation of the voltage stress over time determines the gate-oxide breakdown. Thus, the DC stress is more serious than the AC stress (transient stress). For the DC stress and the defeat-free gate oxide, equation 1.3 can be simplified as equation 1.4, where tox is the thickness of the gate oxide.

0 exp ox BD ox G t t V τ ⎛ ⋅ ⎞ = ⋅ _⎜ ⎝ ⎠⎟ (1.4) As expressed in equation 1.4, the operating voltage of devices must be scaled down to keep the same life time when the gate-oxide thickness is scaled down to improve the performance.

1.1.2. Hot-Carrier Degradation

becomes shorter. If the drain-source voltage is not scaled down with the channel length, the electric field between the drain and the source is large so that the electrons in the channel are accelerated to damage the device. The damage by the accelerated electrons degrades the device performance over time or causes the device breakdown instantaneously. Similar to the gate-oxide overstress, the AC hot-carrier stress (transient stress) is less harmful than the DC stress. Lightly doped drain (LDD) structure is used in the advanced processes to allow the higher drain-source voltage without the hot-carrier degradation [10]-[13]. However, the LDD structure increases the series drain resistance, which degrades the speed performance. Thus, the power supply voltage (VDD) maximizes the speed for a fixed reliability level.

As described in sections 1.1.1 and 1.1.2, the power supply voltage (VDD) for a CMOS technology is a trade-off of the speed performance, the power consumption, and the reliability issue. For speed performance, the higher supply voltage makes the device having the larger drain current to charge and to discharge the capacitive load. The gate-oxide breakdown over time and hot-carrier stress set the maximum supply voltage.

1.2. Issues of High-Voltage Circuit Design in Low-Voltage CMOS

Processes

The device dimension of transistor has been scaled toward the nanometer region and the power supply voltage of chips in the nanoscale CMOS technology has been also decreased due to the reliability and power consumption issues [1]. Obviously, the shrunk device dimension makes the chip area smaller to save silicon cost. The lower power supply voltage (VDD) results in lower power consumption. Therefore, chip design quickly migrates to the lower voltage level with the advancement of the nanoscale CMOS technology. Fig. 1.1 shows the scaling trends of the power supply voltage (VDD) and the oxide thickness (tox) [1]. As

shown in Fig. 1.1, the power supply voltage is decreased and the oxide thickness is thinner when the process is scaled down. However, in order to save the chip area or have the speed performance, some circuits are still designed in the same voltage level but fabricated in the advanced (low-voltage) processes [14]-[18]. Besides, some peripheral components or other ICs in an electronic system are still operated at the higher voltage levels, such as 3.3 V or 5 V [19], [20]. In other words, an electronic system could have chips operated at different voltage levels. Thus, some circuits must be design in low-voltage process, but still operated in the

high-voltage or mixed-voltage (high-voltage and low-voltage) environments. However, the gate-oxide breakdown, the hot-carrier degradation, and the leakage current issues may arise in the low-voltage circuits operated in the high-voltage or mixed-voltage environment.

Figs. 1.2 and 1.3 show a CMOS inverter and an NMOS load amplifier realized with low-voltage (2.5-V) devices but operated in high-voltage (5-V) environment, respectively. As shown in Fig. 1.2, transistors MP and MN have the overstress on their gate oxides anytime, and the hot-carrier stress during the signal transitions in the high-voltage environment. As shown in Fig. 1.3, transistors MN1 and MN2 have the gate-oxide overstress and hot-carrier overstress anytime in the high-voltage environment. Fig. 1.4 shows two inverters realized with 2.5-V devices in mixed-voltage (2.5/5-V) interface. As shown in Fig. 1.4, transistors MP2 and MN2 have the gate-oxide overstress and hot-carrier overstress in the mixed-voltage interface. Besides, a leakage path occurs from 5-V power supply to ground through transistors MP2 and MN2. Thus, the circuits realized with the low-voltage devices in the high-voltage or mixed-voltage environment must be designed carefully to prevent the gate-oxide breakdown, the hot-carrier degradation, and the leakage current issues. Some circuits designed with low-voltage devices but applied in high-voltage environment have been reported. Reference [14] has reported a CMOS operational amplifier (OPAMP) fabricated in a 0.13-μm 1-V CMOS process but operated with 2.5-V power supply (VDD=2.5 V) without gate-oxide reliability issue. The analog-to-digital converters (ADCs) realized with low-voltage devices without gate-oxide reliability issue have been reported in [21], [22]. In [15], [16], I/O circuits realized in a 0.25-μm 2.5-V CMOS technology are operated with the power supply voltage of 5.5 V and 7.5 V without gate-oxide overstress, respectively. In [17], a 5.5-V line driver fabricated in a 0.13-µm 1.2-V CMOS technology has been reported. Reference [18] has reported a high-voltage charge pump circuit realized with low-voltage devices without gate-oxide reliability. In [23]-[25], the I/O buffers realized in low-voltage processes for mixed-voltage applications without reliability and leakage issues have been reported. Therefore, in this dissertation, several high-voltage circuits realized with low-voltage devices are presented.

1.3. Organization of This Dissertation

In Chapter 2, a new mixed-voltage I/O buffer realized with only the thin gate-oxide (low-voltage) devices is presented. The new proposed mixed-voltage I/O buffer with simpler

dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25-µm 2.5-V CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications is also presented in this chapter. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers are also compared and discussed. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices can be easily applied in 1×VDD/2×VDD mixed-voltage interface.

In Chapter 3, an input buffer and an output buffer realized with 1-V and 2.5-V low-voltage devices for 3.3-V applications are presented. Due to the high-integration trend of SOC (system-on-a-chip), an electronic system may be integrated into a single chip. Thus, there are digital circuits and analog circuits in a chip. For example, the digital part of a chip is designed with 1-V devices to decrease its power consumption, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. Thus, the traditional I/O circuits are not suitable for this application. An input buffer with the proposed Schmitt trigger circuit in a 0.13-µm 1/2.5-V CMOS process is presented first. Then, an output buffer with the proposed level converter in a 0.13-µm 1/2.5-V CMOS process is also presented in this chapter.

Chapter 4 presents an NMOS-blocking technique for mixed-voltage I/O buffer. Unlike the traditional mixed-voltage I/O buffer design, the mixed-voltage I/O buffer realized with only 1×VDD devices by using the NMOS-blocking technique can receive 2×VDD, 3×VDD, and even 4×VDD input signal without the gate-oxide reliability issue. In this chapter, the 2×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation of the NMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.

Chapter 5 presents a new charge pump circuit with consideration of gate-oxide reliability issue. Because the charge transfer switches of the new proposed charge pump circuit can be fully turned on and turned off, as well as the output stage doesn’t have the

threshold drop problem, its pumping efficiency can be higher than that of the prior designs. The gate-drain and the gate-source voltages of all devices in the proposed charge pump circuit don’t exceed VDD, so the proposed charge pump circuit doesn’t suffer the gate-oxide reliability problem. Besides, the proposed charge pump circuit has two pumping branches pumping the output node alternately so the output voltage ripple is small. In this work, two test chips have been implemented in a 0.35-µm 3.3-V CMOS process to verify the proposed charge pump circuit. The measured output voltage of the new proposed 4-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD=3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.

Chapter 6 presents an on-chip ultra-high-voltage charge pump circuit designed with the polysilicon diodes in low-voltage standard CMOS processes. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard (bulk) CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-µm 2.5-V standard CMOS process. The measured output voltage of the 12-stage charge pump circuit with 2.5-V power supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in the 0.25-µm 2.5-V standard CMOS process.

Chapter 7 summarizes the main results of this dissertation. Then, some suggestions for the future works are also addressed in this chapter.

Table 1.1

Key Features of the Semiconductor Scaling Trend (High-Performance Logic Technology) [1]

2005 2006 2007 2008 2009 2010 2011 2012

Gate Length, L (nm) 32 28 25 22 20 18 16 14

Oxide Thickness, tox(Å) 12 11 11 9 7.5 6.5 5 5

Power Supply Voltage, VDD (V)

1.1 1.1 1.1 1 1 1 1 0.9

Threshold Voltage, Vt (mV)

195 168 165 160 159 151 146 148

NMOS Drain Current (μA/μm)

Fig. 1.1. Scaling trends of the oxide thickness and the power supply voltage [1].

Fig. 1.3. An NMOS load amplifier realized with 2.5-V devices in 5-V environment.

Fig. 1.4. Two CMOS inverters realized with 2.5-V devices in 2.5/5-V mixed-voltage interface.

CHAPTER 2

Mixed-Voltage I/O Buffers With Only Thin

Gate-Oxide Devices

In this chapter, the prior designs of mixed-voltage I/O buffers are overviewed first. Then, two new mixed-voltage I/O buffers realized with only thin-oxide devices are presented [26]. The new proposed mixed-voltage I/O buffer 1 with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer 1 has been fabricated and verified in a 0.25-µm CMOS process to serve 2.5/5-V I/O interface.

The subthreshold leakage problem is more serious in the advanced CMOS processes, such as the 0.13-µm CMOS process. Therefore, the new proposed mixed-voltage I/O buffer 2 for high-speed applications is also presented to alleviate this problem. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers (new proposed circuits and prior arts) are also compared and discussed. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices can be easily applied in 1×VDD/2×VDD mixed-voltage interface.

2.1. Issues of Mixed-Voltage I/O Interface

The conventional tri-state I/O buffer with 2.5-V gate-oxide devices in a 0.25-µm CMOS process is shown in Fig. 2.1, where the power supply voltage (VDD) is 2.5 V. However, the input signal at the I/O pad in the mixed-voltage I/O interface may rise up to 5 V in the tri-state input (receive) mode. In the receive mode, the gate voltages of the pull-up PMOS device and the pull-down NMOS device in the I/O buffer are traditionally controlled at 2.5 V and 0 V to turn off the pull-up PMOS device and the pull-down NMOS device by the pre-driver circuit, respectively. When the input signal at the I/O pad rises up to 5 V in the tri-state input mode, the parasitic drain-to-well pn-junction diode in the pull-up PMOS device will be forward biased. Therefore, an undesired leakage current path flows from the I/O pad

to the power supply voltage (VDD) through the parasitic pn-junction diode. Besides, because the gate voltage of the pull-up PMOS device is 2.5 V and the input signal at I/O pad is 5 V, the pull-up PMOS device will be turned on in such tri-state input mode to conduct another undesired leakage current path from the I/O pad to the power supply voltage (VDD). Such undesired leakage currents cause not only more power consumption in the electronic system but also malfunction in the whole electronic system.

Moreover, because the gate-drain voltage (Vgd) of the pull-down NMOS device and the gate-source voltage (Vgs) of the input buffer in Fig. 2.1 with 5-V input signal are larger than their voltage levels in the normal operation, such high voltage across the thin gate oxide of the pull-down NMOS device and the input buffer results in the gate-oxide overstress reliability issue [27]-[29]. In addition, the pull-down NMOS device and the input buffer with a 5-V input signal may suffer serious hot-carrier degradation if their drain-source voltages are too large [13].

Fig. 2.2 shows the mixed-voltage I/O buffer with the dual-oxide (thick-oxide and thin-oxide) devices and an external n-well bias voltage. For such mixed-voltage interface applications, the dual-oxide process provided by foundry is used to avoid the gate-oxide reliability problem [30]-[32]. Since the thick oxide can sustain higher gate voltage, the devices which have the gate-oxide reliability problem can be replaced by the thick-oxide devices to prevent the high-voltage overstress on the thin gate oxide. Therefore, the core circuits in a chip are designed with thin-oxide devices to decrease the chip area and power consumption, but the I/O circuits are designed with thick-oxide devices to avoid the gate-oxide reliability issue. In order to avoid leakage current path from the I/O pad to the power supply (VDD) through the parasitic drain-to-well pn-junction diode in the pull-up PMOS device, the body terminal of the pull-up PMOS must be connected to an extra pad that provides a higher external voltage (VDDH) to bias the body of the pull-up PMOS device. In addition, a gate-tracking circuit is needed to avoid the leakage current path induced by the incorrect conduction of the pull-up PMOS device.

Although the traditional mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias can be used to solve the aforementioned problems, there are still some limitations in this I/O buffer. Using an external bias voltage needs an extra pad to provide another power supply (VDDH), the silicon area and the cost of the whole system are increased. The threshold voltage of the thick-oxide devices is so high that their driving capacities are decreased when their gates are controlled by the pre-driver circuit with low-voltage devices. In addition, because the body terminal of the pull-up PMOS device is

connected to a higher voltage (VDDH), the threshold voltage of the pull-up PMOS device is also increased due to the body effect. Because the driving capacity is decreased, the larger device dimension is required for the pull-up PMOS device to support the desired driving specifications. In turn, it increases the silicon area for such I/O buffer. Therefore, the mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias is unsuitable for the low-cost commercial ICs. Considering these limitations, several mixed-voltage I/O buffers have been reported in [23]-[25], [33], [34], which will be overviewed in this chapter.

2.2. Overview on the Prior Designs of Mixed-Voltage I/O Buffers

2.2.1. Design Concept of Mixed-Voltage I/O Buffers With Thin-Oxide Devices

Fig. 2.3 shows the mixed-voltage I/O buffer realized with thin-oxide devices, a dynamic n-well bias circuit, and a gate-tracking circuit. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. In a 0.25-µm CMOS process, the power supply voltage (VDD) is 2.5 V and the threshold voltage of the devices is about 0.6 V. Because the gate terminal of transistor MN0 is connected to 2.5 V (VDD), the drain voltage of transistor MN1 is about 1.9 V (2.5–0.6=1.9) when the input signal at the I/O pad is 5 V in the tri-state input mode. Hence, the gate-drain voltages and the gate-source voltages of the stacked NMOS devices, MN0 and MN1, are limited below 2.5 V even if the input signal at the I/O pad is 5 V. Therefore, the stacked NMOS devices, MN0 and MN1, can solve the gate-oxide reliability problem.

The gate-tracking circuit shown in Fig. 2.3 is used to prevent the leakage current path due to the incorrect conduction of the pull-up PMOS device when the input signal at the I/O pad is higher than VDD. In the transmit mode, the gate-tracking circuit must transfer the signal from the pre-driver circuit to the gate terminal of the pull-up PMOS device exactly. In the tri-state input mode (receive mode) with 5-V input signal, the gate-tracking circuit will charge the gate terminal of the pull-up PMOS device to 5 V to turn off the pull-up PMOS device completely, and to avoid the leakage current from the I/O pad to the power supply (VDD). On the contrary, the gate-tracking circuit will keep the gate terminal of the pull-up PMOS device at 2.5 V to turn off the pull-up PMOS device completely, and to prevent the overstress on the gate oxide of the pull-up PMOS device, when the input signal at the I/O pad is 0 V in the tri-state input mode.

The dynamic n-well bias circuit shown in Fig. 2.3 is designed to prevent the leakage current path due to the parasitic drain-to-well pn-junction diode in the pull-up PMOS device. In the transmit mode, the dynamic n-well bias circuit must keep the floating n-well bias at 2.5 V. So, the threshold voltage of the pull-up PMOS device isn’t increased by the body effect. In the tri-state input mode with a 5-V input signal, the dynamic n-well bias circuit will charge the floating n-well to 5 V to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. When the input signal at the I/O pad is 0 V, the dynamic n-well bias circuit will bias the floating n-well at 2.5 V.

Because the floating n-well is clamped to 2.5 V or 5 V through the parasitic diodes by some dynamic n-well bias circuits [24], [33], [34], the voltage on the floating n-well will be a little lower than 2.5 V or 5 V. The lower floating n-well voltage results in the lower threshold voltage of the pull-up PMOS transistor. Thus, the subthreshold leakage current becomes large when the pull-up PMOS transistor is in off state. If the given process has serious subthreshold leakage issue, such as the 0.13-μm or below processes, the dynamic n-well bias circuit must clamp the floating n-well directly to the desired voltage level by the MOS transistor to decrease the subthreshold leakage.

As shown in Fig. 2.3, the extra transistors, MN2 and MP1, are added in the input buffer. Transistor MN2 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV. Because the gate terminal of transistor MN2 is connected to the power supply voltage (VDD), the input terminal of inverter INV will rise up to 1.9 V (2.5–0.6=1.9) when the input signal at the I/O pad is 5 V in the tri-state input mode. Then, transistor MP1 is used to pull up the input node of inverter INV to 2.5 V when the output node of inverter INV is pulled down to 0 V. Thus, the gate-oxide reliability occurring in the input buffer can be solved.

2.2.2. Prior Designs of Mixed-Voltage I/O Buffers

Fig. 2.4 re-draws the mixed-voltage I/O buffer with stacked pull-up PMOS devices reported in [33]. Signal OE is the output-enable control signal. In the transmit mode, transistor MN1 is turned on and transistor MP2 is turned off, so that this I/O buffer drives the I/O pad according to the output signal Dout. In the tri-state input mode, transistor MN1 is turned off and transistor MP2 is turned on by the control signal OE at logic zero. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP1 and the floating n-well are

pulled up to 5 V through transistor MP2 and the parasitic drain-to-well pn-junction diode in transistor MP0 to prevent the undesired leakage current paths from I/O pad to power supply voltage (VDD), respectively. Although this I/O buffer is simple, transistors MN0, MN1, and MP2 have the gate-oxide reliability problem in the tri-state input mode when the input signal has a 5-V voltage level. Besides, because the stacked PMOS devices with the floating n-well to prevent the leakage current is applied to this I/O buffer, the PMOS devices in stacked configuration occupy more silicon area.

Fig. 2.5 re-draws another mixed-voltage I/O buffer with stacked pull-up PMOS devices and stacked pull-down NMOS devices [34]. This I/O buffer uses transistors MP2, MN3, and MN4 as the gate-tracking circuit and transistors MP0, MP3, and MP4 as the dynamic n-well bias circuit. In the tri-state input mode with the control signal OE at GND, transistor MN4 is turned off and transistor MP2 is turned on. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP3 is biased at 5 V through transistors MP0 and MP2 to avoid the undesired leakage current path due to the incorrect conduction of transistor MP3. The floating n-well is biased at ~5 V through the parasitic drain-to-well pn-junction diode of transistor MP0. In the transmit mode with the OE control signal at VDD, transistor MN4 is turned on so that transistor MP3 is turned on, and transistor MP2 is kept off. Hence, this I/O buffer drives the I/O pad according to the output signal Dout. When the signal at the I/O pad is 0 V, the floating n-well is biased at 2.5 V through transistor MP4. When the input signal at the I/O pad is 2.5 V, the floating n-well is biased at ~2.5 V through the parasitic source-to-well pn-junction diodes of transistors MP3 and MP4. However, transistor MP2 has the gate-oxide reliability problem when the input signal at the I/O pad is 5 V in the tri-state mode. Besides, because the I/O buffer uses two PMOS devices, MP0 and MP3, in stacked configuration to drive the I/O pad, the stacked devices occupy more silicon area.

The mixed-voltage I/O buffer with a depletion PMOS device is re-drawn in Fig. 2.6 [23]. The depletion PMOS device MP2 in the I/O buffer is used as the gate-tracking circuit. In the tri-state mode, if the input signal at I/O pad is 5 V, the gate voltage of transistor MP0 is biased at 5 V through the depletion PMOS device MP2 to avoid the undesired leakage current path through the transistor MP0. This I/O buffer uses an extra pad that is connected to 5-V power supply (VDDH) to avoid the undesired leakage current path through the parasitic drain-to-well pn-junction diode. However, using the depletion device increases mask layer and process modification. Thus, the fabrication cost of such I/O buffer design will be increased. In addition, using the extra n-well bias (VDDH) not only degrades the driving capacity of output device MP0 due to the body effect, but also increases the system cost.

Fig. 2.7 re-draws the mixed-voltage I/O buffer realized with only thin-oxide devices reported in [24]. In Fig. 2.7, the gate-tracking circuit and the dynamic n-well bias circuit are formed by transistors MP1, MP2, MP3, MP4, MN2, MN3, MN4, and MN5. In the transmit mode with signal OE at logic “1”, transistor MN4 is turned on to keep transistors MP3 and MP4 on. Thus, this I/O buffer drives the I/O pad according to signal Dout. Besides, because transistor MP3 is turned on, the floating n-well is biased at 2.5 V by transistor MP3 in the transmit mode. In the tri-state input mode with signal OE at logic “0”, transistor MN4 is kept off. If the input signal at the I/O pad is 5 V, the gate voltages of transistors MP0 and MP4 are biased at 5 V through transistor MP1 and MP2 to avoid the undesired leakage paths through the transistors MP0 and MP4. Besides, the floating n-well is also biased at ~5 V to avoid the undesired leakage path through the parasitic drain-to-well pn-junction diode of transistor MP0 when the voltage at the I/O pad is 5 V in tri-state input mode. When the input signal at the I/O pad is 0 V in the tri-state input mode, transistor MN3 is turned on to keep transistor MP3 on. So, the floating n-well is biased at 2.5 V.

Another mixed-voltage I/O buffer realized with only thin-oxide devices is re-drawn in Fig. 2.8 [25]. The gate-tracking circuit in Fig. 2.8 is composed of transistors MN3, MN4, MP2, MP3, and MP4. The dynamic n-well bias circuit in Fig. 2.8 is formed by transistors MN5, MP5, MP6, and MP7. Besides, the body terminals of all PMOS transistors in the gate-tracking circuit and the dynamic n-well bias circuit are connected to the floating n-well. Such I/O circuit shown in Fig. 2.8 can overcome the gate-oxide reliability problem and avoid the undesired leakage paths. However, too many devices are used to realize the desired functions of the gate-tracking circuit and the dynamic n-well bias circuit. More devices used in the mixed-voltage I/O buffer often cause more complex metal routing connection in the I/O cells.

2.3. New Mixed-Voltage I/O Buffer 1

2.3.1. Circuit Implementation

Fig. 2.9 shows the new proposed mixed-voltage I/O buffer with the new dynamic n-well bias circuit and gate-tracking circuit. The new proposed I/O buffer is realized by only the thin gate-oxide devices, and occupies smaller silicon area than the prior designs of mixed-voltage I/O buffers. When the tri-state control signal OE is at 2.5 V (logic “1”), the new

mixed-voltage I/O buffer is operated in the transmit mode. The signal at the I/O pad rises or falls according to signal Dout, which is controlled by the internal circuits of IC. The lower output port of the pre-driver circuit is directly connected to the gate terminal of the pull-down NMOS device, MN1. The upper output port of the pre-driver circuit is connected to the gate terminal of the pull-up PMOS device, MP0, through the gate-tracking circuit. If the voltage level at the upper port is 0 V, the signal can be fully transmitted to the gate terminal of the pull-up PMOS device MP0 through transistor MN2, and the signal at the I/O pad is pulled up to 2.5 V. Besides, transistor MP4 is also turned on to bias the floating n-well at 2.5 V. When the voltage level at the upper port is 2.5 V, the gate terminal of transistor MP0 is charged to VDD–|Vtp| through transistor MN2 first. Consequently, the voltage at the I/O pad and the gate voltage of transistor MP1 are discharged to 0 V through transistors MN0 and MN1. Transistor MP1 is turned on until the gate terminal of transistor MP2 is discharged to |Vtp|. At this moment, transistor MP2 is turned on to continually pull the gate voltage of transistor MP0 up to 2.5 V. The pull-up PMOS device MP0 can be completely kept off. The floating n-well is also biased at ~2.5 V through the parasitic pn-junction diodes of transistors MP0 and MP4 at this moment.

When the proposed I/O buffer is operated in the tri-state input (receive) mode, the upper and lower output ports of the pre-driver circuit are kept at 2.5 V and 0 V, respectively, to turn off transistors MP0 and MN1. Signal Din rises or falls according to the signal at the I/O pad in the tri-state input mode. In order to prevent the undesired leakage current from the I/O pad to the power supply (VDD) through the pull-up PMOS device MP0, transistor MP3 is used to track the signal at the I/O pad and to control the gate voltage of transistor MP0. When the voltage level at the I/O pad exceeds VDD+|Vtp|, such as 5 V, transistor MP3 is turned on to charge the gate terminal of transistor MP0 up to 5 V. Transistor MP0 is completely turned off to prevent the leakage current through its channel. Transistor MP4 is also turned off and the floating n-well is biased at 5 V through the parasitic pn-junction diode. Thus, there is no leakage current path from the I/O pad to the power supply (VDD). Besides, transistor MP1 is also turned on to keep transistor MP2 off in order to prevent another leakage path from the gate terminal of transistor MP0 to the upper port of the pre-driver, when the signal at the I/O pad is 5 V.

Transistors MN0 and MP5 with inverter INV are used to transfer the input signal from the I/O pad to the internal node Din in the tri-state input mode. Transistor MN0 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV. Because the gate terminal of transistor MN0 is connected to the power supply voltage (2.5 V), the input

voltage of inverter INV is limited to 1.9 V (2.5–0.6=1.9) when the voltage level at the I/O pad is 5 V. Then, transistor MP5 will pull the input node of inverter INV up to 2.5 V when the output node of inverter INV is pulled down to 0 V. The signal at the I/O pad can be successfully transferred to the internal input node Din. This I/O buffer can be correctly operated with neither gate-oxide reliability problem nor any circuit leakage issue in the tri-state input mode.

2.3.2. Simulation and Experimental Results

A 0.25-µm 2.5-V CMOS device model is used to verify the design of the new proposed mixed-voltage I/O buffer by HSPICE simulation. Figs. 2.10(a) and 2.10(b) show the simulated waveforms of the new proposed mixed-voltage I/O buffer with a 20-pF output load at the pad and 50-MHz I/O signal in the transmit mode and in the tri-state input mode, respectively. As shown in Fig. 2.10(a), the new proposed mixed-voltage I/O buffer can successfully drives the I/O pad according to signal Dout in the transmit mode. As shown in Fig. 2.10(b), the new proposed mixed-voltage I/O buffer can successfully transfer the signal at the I/O pad to the signal Din when it receives the 5-V signals in the tri-state input mode. This simulation also verifies that the gate-drain voltages (Vgd) and gate-source voltages (Vgs) of all devices in the new proposed mixed-voltage I/O buffer do not exceed 2.5 V. Fig. 2.10(b) only shows the gate-drain voltage (Vgd) of the pull-up PMOS device MP0. With the new gate-tracking circuit, the Vgd of the pull-up PMOS device MP0 is always controlled within the normal operation voltage (VDD). Thus, the gate-tracking circuit can solve the gate-oxide reliability problem in the new proposed mixed-voltage I/O buffer.

Fig. 2.11 shows the die photograph of the new proposed mixed-voltage I/O buffer fabricated in a 0.25-µm 2.5-V 1P5M CMOS process. The measured waveforms of the new proposed mixed-voltage I/O buffer with 1-MHz I/O signal in the transmit mode, the tri-state input mode with 2.5-V input, and the tri-state input mode with 5-V input are shown in Figs. 2.12(a), 2.12(b), and 2.12(c), respectively. As shown in Figs. 2.12(a), 2.12(b), 2.12(c), the new proposed mixed-voltage I/O buffer can be successfully operated in such a 2.5/5-V mixed-voltage I/O environment. The maximum operation frequency of the proposed I/O buffer depends on the output load and the device size of output circuit. Typically, the proposed mixed-voltage I/O buffer in this work has been successfully verified in silicon that can be operated up to 200 MHz with 20-pF load.

2.4. New Mixed-Voltage I/O Buffer 2

2.4.1. Circuit Implementation

The floating n-well of the proposed mixed-voltage I/O buffer 1 in Fig. 2.9 is biased at ~2.5 V and ~5 V through the parasitic pn-junction diode in the transmit mode with 0-V output signal and in the receive mode with 5-V input signal, respectively. Thus, the voltage level of the floating n-well may be coupled with transient noise when the operating frequency of the mixed-voltage I/O buffer becomes higher. The lower floating n-well voltage results in the lower threshold voltage (Vtp) of the pull-up PMOS, so that the subthreshold leakage current becomes large when the pull-up PMOS is in off state. Considering the coupled noise and the subthreshold leakage current issue due to the floating n-well, another new modified design of the proposed mixed-voltage I/O buffer without n-well floating is shown in Fig. 2.13. Comparing to the design in Fig. 2.9, the gate of transistor MP4 in Fig. 2.13 is connected to the gate of transistor MP2. Besides, two extra NMOS devices, MN3 and MN4, are added to pull the gate voltage of transistor MP4 to 0 V when the I/O buffer in Fig. 2.13 is operated in the transmit mode. In Fig. 2.13, transistor MN3 is used to protect transistor MN4 without the gate-oxide overstress, because the gate voltage of transistor MP4 may be as high as 5 V in the tri-state input mode. In the transmit mode, the gate voltage of transistor MP4 in Fig. 2.13 is pulled down to 0 V through transistors MN3 and MN4. Transistor MP4 is always turned on to bias the floating n-well at 2.5 V whenever the signal at I/O pad is 2.5 V or 0 V. In the receive mode with 5-V input signal, another PMOS device MP6 is turned on to bias the floating n-well at 5 V. Thus, whenever the proposed mixed-voltage I/O buffer 2 is in the transmit mode or the receive mode, the floating n-well is biased at 2.5 V or 5 V directly. The subthreshold leakage problem can be completely solved in the new proposed mixed-voltage I/O buffer 2.

2.4.2. Simulation Results

The proposed mixed-voltage I/O buffer 2 is also simulated in a 0.25-µm 2.5-V CMOS process. Figs. 2.14(a) and 2.14(b) show the simulated waveforms of the proposed mixed-voltage I/O buffer 2 operating in the transmit mode and the tri-state input mode,