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Investigation of Hot-Carrier Stress Effect on High-Frequency Performance of Laterally
Diffused Metal–Oxide–Semiconductor Transistors
View the table of contents for this issue, or go to the journal homepage for more 2012 Jpn. J. Appl. Phys. 51 02BC12
(http://iopscience.iop.org/1347-4065/51/2S/02BC12)
Investigation of Hot-Carrier Stress Effect on High-Frequency Performance
of Laterally Diffused Metal–Oxide–Semiconductor Transistors
Kun-Ming Chen1, Zong-Wen Mou2, Hao-Chung Kuo2, Chia-Sung Chiu1, Bo-Yuan Chen1, Wen-De Liu1, Ming-Yi Chen3, Yu-Chi Yang3, Kai-Li Wang3, and Guo-Wei Huang1;4
1National Nano Device Laboratories, Hsinchu 300, Taiwan
2Department of Photonics, National Chiao Tung University, Hsinchu 300, Taiwan 3United Microelectronics Corporation, Hsinchiu 300, Taiwan
4Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
Received September 16, 2011; accepted November 1, 2011; published online February 20, 2012
The hot-carrier stress effects on the high-frequency performance characteristics of laterally diffused metal–oxide–semiconductor (LDMOS) transistors were investigated. A constant bias channel hot-carrier stress was applied at room temperature. After applying 3 h of hot-carrier stress, the on-resistance and saturation drain current degradations are 18 and 9%, respectively. However, the degradations of the cutoff frequency and maximum oscillation frequency were less than 2% when the devices were biased before the onset of quasi-saturation. In addition, we found that the degradations of high-frequency parameters are not related to the change in transconductance but to the changes in gate capacitances. Finally, S-parameter variations under hot-carrier stress were also examined in this study. The observations of S-parameter variations are important for RF power amplifier design. # 2012 The Japan Society of Applied Physics
1. Introduction
The rapid growth of wireless communication product markets has created a huge demand for low-cost, high-efficiency, and good-linearity RF power amplifiers. Among power devices, laterally diffused metal–oxide–semiconduc-tor (LDMOS) transismetal–oxide–semiconduc-tors are the most attractive in cost and potential for improvements in performance and integration. LDMOS transistors have been widely used in RF power amplifier modules for a high frequency range up to 3.8 GHz.1–3) Because the LDMOS used in power amplifiers is operated at a high drain voltage while carrying a high current, it could be vulnerable to hot carrier injection and trapping. Therefore, hot-carrier instability is one of the major reliability issues in an LDMOS and has widely attracted attention in recent years.4–7)Owing to the existence of a drift region, the mechanisms of hot-carrier-induced degradation in LDMOS transistors differ substantially from that in standard complementary metal–oxide–semiconductor (CMOS) transistors. The degradation mechanism depends on the device structure and stress condition. Generally, the hot-carrier degradation is associated with the effects of hot hole/electron injection in the channel region and/or the drift region of LDMOS transistors.
For RF power circuit design, it is important to evaluate the hot-carrier stress effects on the high-frequency character-istics of power transistors to predict stress-induced circuit performance drifts. Although the hot-carrier reliability of LDMOS transistors has been investigated in many studies, there are only a few reports that address the hot-carrier stress effects on RF behaviors,8–10)particularly on the degradation of S-parameters and the RF figures of merit, such as cutoff frequency ( fT) and maximum oscillation frequency ( fmax). Previously, hot-carrier-induced fT or S-parameter degrada-tions were shown only to verify the reliability improvement of a new device structure8,9) or compare the measurement results of different aging test methods.10) However, the mechanisms of high-frequency parameter degradations were not discussed in detail. In this paper, we present the experimental results of the high-frequency characteristics of
LDMOS transistors under hot-carrier stress. It was observed that fT decreases and fmax remains almost unchanged after applying stress under the bias conditions of RF-power-amplifying applications. The degradation mechanisms of the high-frequency parameters are discussed in detail by analyzing the changes in gate capacitances. Finally, S-parameter variations under hot-carrier stress are also shown in this paper.
2. Experiments
The n-channel LDMOS transistors used in this study were fabricated by a 0.5m CMOS-DMOS process with a gate oxide thickness of 135 A.11)The off-state breakdown voltage is about 41 V. As illustrated in Fig. 1, the devices have a lightly doped N-well drift region under the field oxide (FOX). The effective channel length and drift length are 1.1 and 2m, respectively. The source and p-body contacts are tied together to eliminate extra surface bond wires to reduce the source inductance and improve the RF performance in a power amplifier configuration.12) To monitor the body current, devices with separate source and p-body contacts were also fabricated. The devices under test have a multifinger gate configuration featuring eight fingers with a total width of 80m.
A constant bias hot-carrier stress was applied with a gate voltage of 2.5 V and a drain voltage of 28 V at room temperature. The applied gate voltage corresponds to the maximum body current. The stress tests were interrupted periodically to measure the degradation of device electrical parameters. The S-parameters were measured on chip using
Fig. 1. (Color online) Schematic cross section of an LDMOS transistor.
an Agilent 8510 network analyzer from 100 MHz to 15 GHz. After de-embedding the parasitic pad effects, the ac current gain (H21) and unilateral power gain (U) were calculated to extract fT and fmax, respectively.
3. Results and Discussion 3.1 DC characteristics
Figure 2 shows the effects of hot-carrier stress on the dc characteristics of an LDMOS. In Fig. 2(a), the threshold voltage is found to exhibit no degradation after applying stress (<0:5 mV), which means that there is no damage on the source side of the channel. When the device operates in the linear region (drain voltage VDS¼ 0:1 V), the maximum value of linear transconductance (gm,lin) shows an approxi-mately 3% degradation, probably owing to the interface trap generation near the drain side of the channel. When the device operates in the saturation region (VDS¼ 12 V), the drain current (ID) and transconductance (gm) degradations are not observed (<0:2%) before the quasi-saturation effect occurs (VGS < 3 V). In this bias range, the drain current is dominated by the channel current. In addition, the pinch-off region on the drain side of the channel is created; thus, the generated interface traps in the channel would only slightly affect the carrier mobility. At high gate voltages, the device operation enters the quasi-saturation region, and ID and gm
decrease significantly after applying stress. In this operation region, N-well drift resistivity has a large impact on the device characteristics. During hot-carrier stress, the gener-ated interface traps in the drift region may capture the electrons and thus increase the surface scattering, leading to the reduction in carrier mobility.4–6)
The severe hot-carrier-induced current degradation in the quasi-saturation region can also be observed in the device output characteristics, as depicted in Fig. 2(b). At high drain voltages, IDdegradation decreases as the current is pushed deeper in the silicon; hence, the trap-induced surface scattering also decreases. From Fig. 2(b), we extracted the on resistance (RON) and saturation drain current (ID,sat) at VDS ¼ 0:5 and 12 V, respectively, under the gate voltage condition VGS¼ 5 V. We found that RONincreases and ID,sat decreases upon applying hot-carrier stress. As shown in Fig. 3, the degradations of RON and ID,satare about 18 and 9%, respectively, after applying 3 h of stress; they are higher than the degradation of gm,lin, suggesting that the stress-induced damage in the drift region is more serious than that in the channel region. In addition, the slopes of the RONand
ID,satcurves in Fig. 3 are in the 0.3–0.4 range, which is close
to that reported in ref.4. Moens et al. pointed out that the hot-carrier-induced interface traps in the drift region are produced at the source-side bird’s beak of the FOX when the stress condition corresponds to the maximum body current.4) Since the hot carriers affect the dc characteristics of an LDMOS transistor, they may also result in the degradation of high-frequency performance.
3.2 fT andfmax
The gate voltage dependence of fT under hot-carrier stress is shown in Fig. 4. The degradation of the maximum value of fT is1:9% after applying 3 h of stress. This degradation is much lower than those of RON and ID,sat, owing to the different measurement biases. This result indicates that hot-carrier instability would be less serious when the LDMOS is used in RF power amplifiers than when the LDMOS is used in power switching circuits. In addition, we found that although gm is unchanged by the stress at the peak fT [see 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 10-6 10-5 10-4 10-3 10-2 1 2 3 4 5 6 7 8 VDS=12 V
Drain Current (A)
Gate Voltage (V) VDS=0.1 V
W=80 μm before stress after stress Transconductance (mA/V)
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30
Drain Current (mA)
Drain Voltage (V) before stress after stress W=80 μm VGS=1 - 5 V, 0.5 V step (a) (b)
Fig. 2. (Color online) (a) ID–VGSand (b) ID–VDScharacteristics of an
LDMOS measured before and after applying 3 h of hot-carrier stress.
101 102 103 104 0.1 1 10 100 ΔRON/RON -ΔID,sat/ID,sat -Δgm,lin/g m,lin Degradation (%) Stress Time (s)
Fig. 3. (Color online) Degradations of RON, ID,sat, and gm,linwith
hot-carrier stress time. RONand ID,satare extracted at VDS¼ 0:5 and 12 V,
respectively, under VGS¼ 5 V. gm,linis the maximum transconductance at
VDS¼ 0:1 V.
K.-M. Chen et al. Jpn. J. Appl. Phys. 51 (2012) 02BC12
Fig. 2(a)], fT still exhibits a small degradation. This observation is different from that in metal–oxide–semicon-ductor field-effect transistors (MOSFETs), where gm plays an important role in fT degradation.13)The cutoff frequency can be expressed as a function of gm and gate capacitances, that is,
fT ¼
gm 2ðCgsþ CgdÞ
; ð1Þ
where Cgs is the gate-to-source capacitance and Cgd is the gate-to-drain capacitance. Because gm is unchanged by the stress, the degradation of fTmay be attributed to the changes in gate capacitances.
The changes in Cgs and Cgd under hot-carrier stress are shown in Fig. 5. The values of the gate capacitances are extracted from the Y-parameters at low frequencies. Before quasi-saturation (VGS< 3 V), Cgs increases with increasing stress time, whereas Cgd decreases. The increase in Cgs under hot-carrier stress was also observed in MOSFET devices,14) and this phenomenon can be explained by the change in channel surface potential owing to the negative trap charges appearing near the drain side of the channel. However, in MOSFETs, Cgd was nearly unchanged under hot-carrier stress as the device was operated in the saturation
region.13,14)The different results between MOSFETs and our device are due to the existence of a drift region. In LDMOS transistors, a large part of Cgd comes from the drift region. The stress-induced negative interface charges in the drift region lead to positive mirror charges in the silicon, thus reducing the effective top N-well concentration. As such, the depletion layer width in the drift region increases and thus Cgd decreases. By plotting the degradations of cutoff frequency and total gate capacitance (Cgg¼ Cgsþ Cgd) as functions of stress time (see Fig. 6), we found that the changes in fT and Cgg are similar. This result confirms that the fT degradation is dominated by the change in gate capacitance.
When the gate voltage increases and reaches the quasi-saturation region, both the transconductance and gate capacitance markedly change [see Figs. 2(a) and 5] owing to the increased drain resistance after stress. As a result, fT exhibits a large stress-induced degradation at high gate voltages. It was also noted that both Cgs and Cgd increase with stress time in this bias range. In LDMOS transistors, because the inversion charges may be injected from the intrinsic MOSFET to the depleted area of the drift region, Cgs and Cgd increase with increasing gate voltage, and Cgs even increases over the limit of inversion.15)The increase in gate capacitance with gate voltage may become more apparent as the drain resistance increases. Therefore, the increases in Cgs and Cgd under stress might be mainly attributed to the increased drain resistance.
Figure 7 shows the degradation of maximum oscillation frequency under hot-carrier stress. The maximum value of fmax is nearly unchanged with stress time (<0:5%). fmax can be expressed as16) fmax¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi fT 8RgCgd s ; ð2Þ
where Rg is the gate resistance. Because the gate resistance is not affected by the hot carriers, we only consider the effects of fT and Cgd on fmax, and the fmax degradation (fmax=fmax) is now written as
fmax fmax ¼ 1 2 fT fT 12 Cgd Cgd : ð3Þ 1.5 2.0 2.5 3.0 3.5 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 Cutof f Frequency (GHz) Gate Voltage (V) Fresh 100 s 1200 s 10800 s VDS=12 V W=80 μm
Fig. 4. (Color online) Measured cutoff frequency as a function of gate voltage for LDMOS under hot-carrier stress.
1.5 2.0 2.5 3.0 3.5 4.0 100 120 140 160 180 200 220 240 260 280 26 28 30 32 34 36 Gate-to-Source Capacitance (fF) Gate Voltage (V) Fresh 100 s 1200 s 10800 s VDS=12 V W=80 μm Gate-to-Drain Capacitance (fF)
Fig. 5. (Color online) Extracted gate capacitances as a function of gate voltage for LDMOS under hot-carrier stress.
10 100 1000 10000 10-2 10-1 100 101 -ΔfT/fT ΔCgg/Cgg Degradation (%) Stress Time (s) W=80 μm VDS=12 V, VGS=2.6 V
Fig. 6. (Color online) Degradations of cutoff frequency and total gate capacitance under hot-carrier stress.
After 3 h of stress, the degradations of fTand Cgdare 1.9 and 2.0%, respectively, at VGS¼ 2:6 V and VDS¼ 12 V. Owing to the similar degradations of fT and Cgd, fmax would not be changed by the hot carriers. At high gate voltages, large fmax degradations are observed owing to the obvious fTreduction and Cgd enhancement.
3.3 S-parameters
Figure 8 shows the S-parameters measured before and after hot-carrier stress versus frequency. The transistor was meas-ured at VGS ¼ 2:6 V and VDS¼ 12 V for the maximum value of fT. Although all S-parameters are affected by the hot carriers, their degradations (1.1–1.3% at 15 GHz) are not as significant as those of RON and ID,sat. As shown in Fig. 8, the stress-induced deviations of the four S-parameters are similar and increase with increasing frequency. These findings differ from the results for MOSFET devices.17,18) In the case of MOSFETs, S21 and S22 change more than S11 and S12 after applying stress. Moreover, the stress-induced deviations of S21 and S22 decrease with increasing fre-quency. This is because the changes in S-parameters are mainly attributed to the changes in the tranconductance and channel conductance of MOSFETs. In our devices, the degradations of S-parameters are due to the changes in Cgs and Cgd.
The observations in hot-carrier-induced S-parameter degradations are very important for power amplifier design. In Fig. 8(a), the reduction in S12implies that the isolation of transistors is improved. Therefore, the degradation of fmaxis less than that discussed previously. It is worthwhile to pay attention to the measured results of S21 and S22. At low frequencies, S21and S22are almost unchanged. This suggests that the tranconductance and channel conductance are not affected by the stress, which is consistent with the measured dc characteristics. As the frequency increases, S21 and thus the voltage gain decrease gradually. Moreover, the increase in S22is observed at high frequencies; this is due to not only the reduction in Cgdbut also the increase in drain resistance. Since S11 and S22change after applying stress, we know that the hot carriers also affect the input and output reflection coefficients of the transistors.
4. Conclusions
In this work, we investigated the hot-carrier stress effects on the high-frequency performance characteristics of LDMOS transistors. After applying stress, the cutoff frequency decreases, while the maximum oscillation frequency remains almost the same when the device operates before the quasi-saturation effect occurs. This observation can be explained by the changes in Cgs and Cgd owing to the generated trap charges in the channel and drift regions, respectively. In addition, we also examined S-parameter variations under hot-carrier stress. Our experimental results showed that the hot carriers affect the voltage gain as well as the input and output reflection coefficients of the LDMOS transistors. However, these degradations are less than those of on-resistance and saturation drain current, indicating that the hot-carrier effect is less serious when the devices are used in RF power amplifying applications.
Acknowledgements
The authors would like to thank the staff members of United Microelectronics Corporation for their helpful comments. This work was supported in part by the National Science Council of R.O.C. through contracts NSC99-2221-E-492-027-MY2. 1.5 2.0 2.5 3.0 3.5 4.0 12 13 14 15 16 17 18
Maximum Oscillation Frequency (GHz)
Gate Voltage (V) Fresh 100 s 1200 s 10800 s VDS=12 V W=80 μm
Fig. 7. (Color online) Measured maximum oscillation frequency as a function of gate voltage for LDMOS under hot-carrier stress.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 S21 S22 S12 before stress after stress Magnitude (dB) Frequency (GHz) S11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 S21 S22 S12 Phase (rad) Frequency (GHz) S11 before stress after stress (a) (b)
Fig. 8. (Color online) (a) Magnitudes and (b) phases of S-parameters before and after applying 3 h of hot-carrier stress. The measurement conditions were VGS¼ 2:6 V and VDS¼ 12 V.
K.-M. Chen et al. Jpn. J. Appl. Phys. 51 (2012) 02BC12
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