[PDF] Top 20 An Area Efficient Low-Voltage 6-T SRAM Cell
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An Area Efficient Low-Voltage 6-T SRAM Cell
... While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve hig[r] ... See full document
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An Area Efficient Low-Voltage 6-T SRAM Cell Using Stacked Silicon Nanowires
... An Area Efficient Low-Voltage 6-T SRAM Cell Using Stacked Silicon Nanowires.. Ya-Chi Huang 1 , Meng-Hsueh Chiang 1 , Sumeet Kumar Gupta 2 , and Shui-Jinn Wang 1.[r] ... See full document
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An Area Efficient Low-Voltage 6-T SRAM Cell Using Stacked Silicon Nanowires
... In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on c[r] ... See full document
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A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
... In this paper, with a unique structure by connecting the source terminal of an NMOS device in the S W cell to the write word line, this 6T SRAM cell can be used to p[r] ... See full document
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Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits
... 8T cell shows an unique reflective trend as indicated by the dashed lines in ...TFET-MOSFET SRAM cell comprising cross-cou- pled inverters, while the WSNMs of MOSFET and TFET 8T cells exhibit ... See full document
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A 45nm dual-port SRAM with write and read capability enhancement at low voltage
... the cell current may be not enough to sense out at a lower VDD ...negative voltage booster as Figure 5 to boost the selected column’s VSS to negative and therefore re-enhance the read current ...In ... See full document
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Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics
... A SRAM cell storing ...evaluates cell stability considering both the static and bias-dependent transient effects, and hence provides a more accurate measure of stability of SRAM cell in ... See full document
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A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System
... corresponding original triangle in the mesh subdivision. Thus, the reflection line will be the same. B. Chip Layout and Comparison Results Concerning the chip layout of the proposed GE architecture, the cell-based ... See full document
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A low-phase-noise area-efficient 3-D LC VCO in standard 0.18-um CMOS technology
... Fig.4 The microphotograph of the 3-D LC VCO. The total die area excluding the testing pad of control voltage is only 0.224 mm 2 . III. R ESULTS AND D ISCUSSION The core of the VCO draws a current of 10 mA ... See full document
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Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells
... and low-Vt SOI SRAM cells. “Cell” Read access time is analyzed by connecting a column of 64 UTB SOI SRAM cells (64 cells per ...differential voltage after the word-line is activated ... See full document
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A Sub-100 mu W Area-Efficient Digitally-Controlled Oscillator Based on Hysteresis Delay Cell Topologies
... C. Nested HDC A general form of nested HDCs (NHDC) is shown in Fig. 3(d). It can be viewed as a cascaded HDC with its internal delay chains composed of cascaded HDCs. A signal transition at the input propagates through ... See full document
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Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation
... SOI SRAM cells for ultralow voltage near subthreshold operation, including RSNM, WSNM, “cell” read access time, time-to-write, and cell ...word-line voltage lowering, bit-line precharge ... See full document
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An implementation of integrable low power techniques for modem cell-based VLSI designs
... several low-power design techniques for VLSI circuitry in nano-scale CMOS ...essential low power techniques such as voltage separation, body bias and power switch are implemented in existent place ... See full document
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AN AREA TIME-EFFICIENT MOTION ESTIMATION MICRO CORE
... Through pipelining and effective manipula- tion of 2's complement arithmetic, complexity of the micro architecture is kept to its lowest, while time spent for a combined subtraction[r] ... See full document
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A low-error and area-time efficient fixed-width booth multiplier
... In many digital signal processing (DSP) applications such as digital filters [6, 7] and wavelet transform, it is desirable to maintain fixed-width output word through tihe arithmetic ope[r] ... See full document
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A low-voltage fully-integrated 4.5-6-GHz CMOS variable gain low noise amplifier
... network, acting as a high impedance element at resonant frequency to force signal passing through the followed PMOS for overall small signal gain (IS& In our circ[r] ... See full document
4
An efficient over-the-cell channel router
... 2 depicts the results of partitioning multi-terminal nets into two-terminal subnets and shows the values of zone density and pseudo zone density in a channel.. But if viewing[r] ... See full document
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AN AREA-EFFICIENT MEDIAN FILTERING IC FOR IMAGE VIDEO APPLICATIONS
... Using the shiftable content ad- dress memory architecture, we have developed a very cost- effective hardware solution for median search as well as for d a t a sorting[r] ... See full document
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A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers
... 51 have been widely studied. King and Swartzlander [3] analyzed an adaptive error-compensation bias and proposed an n-bit fixed- width multiplier. In [ l , 21, we generalized[r] ... See full document
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1.5 V CMOS full-swing energy efficient logic (EEL) circuit suitable for low-voltage and low-power VLSI applications
... A 1.5V full-swing energy efficient logic circuit is reported that is suitable for next-generation low-power VLSI applications using a low supply voltage.. Introduction: Fo[r] ... See full document
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