[PDF] Top 20 Architecture design for deblocking filter in H.264/JVT/AVC
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Architecture design for deblocking filter in H.264/JVT/AVC
... Our basic idea is to buffer the 8x4 unfilteredlfiltered pixels of two adjacent 4x4-blocks in an 8x4 pixel array with reconfigurable data path in order to support both hori- zont[r] ... See full document
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Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
... HARDWARE ARCHITECTURE DESIGN FOR VARIABLE BLOCK SIZE MOTION ESTIMATION IN MPEG-4 AVC/JVT/ITU-T H.264.. Yu- Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, and Liang-Gee Chen DSPlIC Design L[r] ... See full document
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An in-place architecture for the deblocking filter in H.264/AVC
... Terms—Deblocking filter, H.264/AVC, VLSI architecture ...used in various video coding standards, such as MPEG-1, MPEG-2, MPEG-4, and ...especially in the low bit ... See full document
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Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
... to design a hardwired encoder for real- time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential al- gorithms in ...loops. ... See full document
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An efficient pipeline architecture for deblocking filter in H.264/AVC
... the H.264/AVC deblocking filter is mainly based on two ...scribed in the previous section, the computation of boundary strength, the threshold value of Alpha and Beta, the table- ... See full document
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Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture
... As for EC/DB stage, modification of algorithm will influence the consistence between encoder and ...demanded for DB to be done in parallel with other stages MB by MB in raster ...arrange ... See full document
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A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC
... software for the other tasks. In this work, we additionally add the accelerator for de-blocking ...filter. In this system, the ARM966 CPU is running at 130MHz and the FPGA module is ... See full document
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Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
... Deblock Filter In our previous work [7], we proposed the architecture for an ...deblock filter. A parallel-in parallel-out FIR filter and an array of 8×4 8-bit shift ... See full document
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Algorithm analysis and architecture design for HDTV applications - a look at the H.264/AVC video compressor system
... and in-loop deblocking filters, is very ...MB in pipelined structure to improve the hardware utilization and through- ...put. For module architecture, the problem of sequential ... See full document
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Design of anMC Interpolation Architecture for H.264 Video Decoder
... (-3.18) For the same reason as FTM filter method, the STM filter using nearest four half-pixel samples to process the intermediate half-pixel sample, and the four half-pixel samples in ... See full document
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High Efficiency Data Access System Architecture for Deblocking Filter Supporting Multiple Video Coding Standards
... operation in frame/field mode d) Field/Frame Mode As described in Section II, the major reason of adopting different filter orders is to simplify the controller of the preload ...is in frame ... See full document
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Hardware architecture design for H.264/AVC intra frame coder
... ABSTRACT In this paper, we contributed a VLSI architecture design for ...system architecture achieves 215 times of speed compared with RISC-based software implementation in terms ... See full document
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VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
... Manufactured in The United States Abstract The H.264/AVC Fractional Motion Estima- tion (FME) with rate-distortion constrained mode decision can improve the rate-distortion efficiency by 2–6 ... See full document
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Hardware architecture design of an H.264/AVC video codec
... methodology for H.264/AVC video codec. The system architecture and scheduling will be ...The design consideration and optimization for its significant modules including ... See full document
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Analysis and architecture design of variable block-size motion estimation for H.264/AVC
... Tree architecture, all distortions of a searching candidate are generated in the same cycle, and by an adder tree, distortions are accumulated to derive the SAD in one ...cycle. In order to ... See full document
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Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC
... Architecture Design of Context-Based Adaptive Variable-Length Coding for ...coding architecture will lead to low throughput and utilization. In this brief, an efficient CAVLC ... See full document
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Analysis and reduction of reference frames for motion estimation in MPEG-4 AVC/JVT/H.264
... we analyze the available information after intra prediction and mo- tion estimation from previous one frame to determine whether it is necessary to search more frames.. The information[r] ... See full document
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Exploiting fine-grain parallelism in the H.264 deblocking filter by operation reordering
... 3. Design Analyzing applications at a finer granularity usually provides additional opportunities for ...parallelization. In H.264, the standard defined orders intersect with each other ... See full document
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Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
... VLSI Architecture Design for H.264/AVC Intra Frame Coder Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, and Liang-Gee Chen, Fellow, IEEE Abstract—Intra prediction with ... See full document
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Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
... listed in Table IV. Because they are all designed for the previous stan- dards, where VBS and MRF are not supported, the parameter of our design is set as the single-iteration 4SS with one reference ... See full document
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