[PDF] Top 20 Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
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Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
... become a Department Manager in the VLSI Design Division of Computer & Communication Research Laboratories (CCL), Industrial Tech- nology Research Institute ...also a Research Advisor ... See full document
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On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
... “ ON ” or “ OFF ” state. To overcome the transient-induced latch- on issue, the ESD-transient detection circuit is added with diode string to adjust its holding ...Because ... See full document
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Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
... that the failure on the traditional power- rail ESD clamp circuit and design A is due to a high trigger current flowing through M p ... See full document
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Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
... investigate the capacitance of different metal-layer capaci- tors, the test devices of MIM and MOM capacitors had been fabri- cated in the silicon chip with a 65 nm CMOS ... See full document
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New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
... been the Chair Professor and Vice President with I-Shou University, Kaohsiung, ...currently a Distinguished Professor with the Department of Electronics Engineering, Na- tional Chiao Tung University, ... See full document
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ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
... EVIEW ON D IODE S TRINGS A. Conventional Diode String in CMOS Technology The cross-sectional view of the conventional four-stage diode string is shown ... See full document
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Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
... IRCUIT The proposed ultra-low-leakage power-rail ESD clamp circuit is shown in ...3. The p-type substrate-triggered sil- icon-controlled rectifier (SCR) ... See full document
9
Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
... investigated in a 0.6-lm CMOS process. By using the substrate-triggered technique, the DTDB, STDB, and STLB devices can provide much higher ESD ro- bustness ... See full document
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Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
... A. ESD Level The ZapMaster ESD tester, produced by Keytek Instrument ...measure the HBM ESD level of the fabri- cated testchips. The failure criterion is generally ... See full document
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Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... overview on ESD protection designs for the mixed-voltage I/O circuits without suffering the gate-oxide reliability ...improve ESD level of the mixed-voltage I/O ... See full document
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High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
... ADVANCED CMOS technologies, the thickness of gate oxide has been scaled down to improve circuit performances with the decreased power supply voltage for low-power appli- ... See full document
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Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
... layer in [25] is compared with the proposed design of this work instead of diode strings in ...of the main benefits of the new proposed power-rail ESD ... See full document
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On-chip ESD protection design by using polysilicon diodes in CMOS process
... to the limitation of using the bulk p–n junction diodes to realize the bridge rectifying circuit, the on-chip ESD protec- tion circuits for pad1 and pad2 are ... See full document
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New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
... VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 × VDD) devices and a silicon-controlled rectifier (SCR) as the main ... See full document
5
ESD protection design for CMOS RF integrated circuits using polysilicon diodes
... Conclusion A novel ESD protection design with stacked polysilicon diodes for RF ICs has been proposed and ...characterized. The polysilicon diode with an un-doped central region ... See full document
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Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
... determining the dimen- sions of ESD protection diodes, whole-chip ESD protection scheme can be realized with the active power-rail ESD clamp circuit ...investigate ... See full document
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Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology
... addition, the latch-on event in BFET2 or Modified3 would vanish by some modifications of layout style and n-well ...Consequently in layout, the width of N+/n-well minority guard rings ... See full document
10
Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
... A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only IxVDD devices for 3xVDD-tolerant mixed-voltage [r] ... See full document
2
Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
... Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology Chih-Ting Yeh, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE Abstract—A ... See full document
8
Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
... AIL ESD C LAMP C IRCUIT A. Circuit Schematic The new proposed power-rail ESD clamp circuits of the ultralow standby leakage are shown in ...as ... See full document
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