Dissertation Organization

With the above-mentioned ESD design challenges, IC industries are eager to have robust ESD protection solutions so as to enhance product yields and stability. This dissertation accordingly focuses on the improvement techniques to HV MOSFETs’ ESD protection levels.

Several new design concepts and practical ESD design solutions that have been realized in commercial IC products are proposed in this dissertation. This dissertation consists of 8 chapters. With the HV N-Well that encloses the nLDMOS, the substrate-triggered technique which is well-known in low-voltage logic technologies is not applicable in the traditional layout method of HV transistors. To alleviate the non-uniform triggering among nLDMOS, a new waffle layout method enabling the body current injection is proposed in chapter 2.

In chapter 3, the safe operating area (SOA) which defines the I-V switching boundaries of a HV transistor is reviewed. SOA characterization methods and improvement methods are discussed in this chapter. The SOA discussion is related to the electrical SOA improvement method in chapter 4 that solves the degraded SOA of an nLDMOS when a silicon controlled rectifier (SCR) is integrated for ESD purposes.

In chapters 5 and 6, there are two fully-silicided ESD solutions that have been implemented on commercial IC products. Designs in chapter 5 enhance ESD protection level

through layout method and are universal to IC products with push-pull output drivers. In chapter 6, the design is specially devised for voltage programming pins that have the fail-safe requirement so as to prevent leakage current when programming internal memories. The ESD design also prevents the latchup-like problem when the programming signal has a fast voltage rise time.

A study to the holding voltage of nLDMOS is included in chapter 7. Holding voltage is a key design consideration for developing high latchup-resistant ESD protection elements. A gradually decreased transistor holding voltage is observed and analyzed by using long-pulse transmission line pulsing (TLP) system [2]. This phenomenon has a negative impact to IC latchup and hence leads to new latchup design considerations.

Chapter 8 summarizes the results of this dissertation and its contribution to future reliability researches. To sum up, this dissertation includes not only new and useful academia ESD research results, but also practical ESD design solutions to the IC industries.

Chapter 2

Waffle Layout Structure With Body-Injected Technology in BCD High-Voltage Processes

2.1. Background

With the thriving applications in silicon ICs, the demands of HV ICs are increasing rapidly [8]. In HV ICs, the power supply voltage (VCC) is often over ten volts or even higher. To fabricate devices to sustain such a high operating voltage, not only the process complexity is increased but also the difficulty to guarantee the reliability of HV devices. ESD is an important and inevitable event ICs during fabrication, packaging, and assembling processes [9]–[12]. ESD protection in HV technology is challenging and has received a lot of attention recently [13]–[16].

To improve the ESD robustness of HV NMOS, several techniques related to process modifications have been reported [16]–[20]. The method of inserting N+ buried layer (NBL) has been used to enhance the ESD robustness of nLDMOS [16]. However, additional process steps and mask layers are needed. Besides, a heavily doped P-type body implantation has been used to avoid the non-uniform triggering of parasitic NPN bipolar junction transistors (BJTs) when a HV NMOS is drawn with large array, i.e. large device dimensions (W/L) [20].

In this chapter, the influence of highly doped P-type boron implantation (PBI) layer to the ESD robustness of nLDMOS is first investigated. The nLDMOS was designed to discharge ESD current through the parasitic BJT inherent in the nLDMOS. A circuit and layout co-design method is then proposed to improve ESD robustness of the nLDMOS [21], [22].

The proposed method exploits the body current injection to improve turn-on uniformity of nLDMOS devices during ESD stresses. Therefore, it does not require process modifications or additional mask layers. The proposed method was verified in a 0.5-m 16-V and a

0.35-m 24-V bipolar CMOS DMOS (BCD) process.

(a)

(b)

Fig. 2.1. (a) Layout diagram and the (b) device cross-sectional view along A-A’ line of an nLDMOS in a 0.5-m 16-V BCD process with the optional PBI layer.

2.2. Effect of P-type Boron Implantation on ESD Performance of High-Voltage nLDMOS

Fig. 2.1(a) shows the traditional (stripe) layout diagram of an nLDMOS in the 0.5-m 16-V BCD process. The nLDMOS in the 0.5-m 16-V BCD process is defined within one

single OD region, so that the gap between N+ drain and the poly gate is the active area.

Device cross-sectional view of the 16-V nLDMOS along A-A’ line in Fig. 2.1(a) is shown in Fig. 2.1(b). A PBI layer is optionally implanted underneath the source N+ and P+ regions in the 16-V nLDMOS to investigate its effectiveness on ESD robustness.

(a)

(b)

Fig. 2.2. (a) Layout diagram and the (b) device cross-sectional view along A-A’ line of the nLDMOS in a 0.35-m 24-V BCD process.

For nLDMOS in the 0.35-m 24-V BCD process, drain and source/body regions are defined in different active areas, as shown in Fig. 2.2(a). The gap between N+ drain and poly gate of the nLDMOS device is a field oxide (FOX) region. Device cross-sectional view along

A-A’ line of the 24-V nLDMOS in Fig. 2.2(a) is shown in Fig. 2.2(b). The FOX gap of the 24-V nLDMOS can avoid the field crowding near the drain of nLDMOS, which, in turn, helps the nLDMOS to sustain the high operating voltage of 24 V. In both 16 and 24 V technologies, the nLDMOS devices are surrounded by HV N-Well [23]; P-Body regions in an nLDMOS are fully separated from the common p-type substrate (P-sub). P+ body pick up at every source region is required to bias the P-Body. Channel lengths are defined by the overlapped region of P-Body and the poly gate.

Fig. 2.3. TLP-measured I-V characteristics of gate-grounded 16-V nLDMOS devices with or without the PBI layer.

To analyze characteristics of devices under HBM ESD stresses, TLP system with 100-ns pulse width has been commonly adopted [24], and Fig. 2.3 shows the TLP-measured I-V characteristics of the 16-V nLDMOS with traditional (stripe) layout style. Both 16-V nLDMOS with and without PBI layer in Fig. 2.3 have the same device dimension (W/L) of 363.6 m/0.35 m with each finger width of 45.45 m. From the TLP measurement results, the bipolar trigger voltage (Vt1) of the gate-grounded 16-V nLDMOS without PBI

implantation is 21.4 V. With the heavily doped PBI to reduce the parasitic P-Body resistance, Vt1 of the gate-grounded 16-V nLDMOS is increased to 23.4 V. Because the bipolar beta gain in the nLDMOS is also suppressed by the PBI layer, holding voltage of the first snapback is slightly increased from 10 to 10.86 V. However, the secondary breakdown current (It2) of the 16-V nLDMOS was found to be degraded from 0.39 to 0.28 A due to the PBI layer.

To explain the degradation on ESD robustness of nLDMOS with PBI, the typical I-V characteristic of a gate-grounded NMOS (ggNMOS) during ESD stresses is depicted in Fig.

2.4. When the voltage across the ggNMOS is higher than the reverse drain/body junction breakdown voltage, drain current of the ggNMOS starts to increase due to the avalanche generation. The junction breakdown (VAV) is typically defined as the voltage corresponding to a 1-A current level of the ggNMOS. Before the avalanche generation current is large enough to forward bias the parasitic body/source junction diode, the ggNMOS acts as a reverse-biased PN junction (HV N-Well/P-Body in Fig. 2.2(b)). Therefore, the voltage keeps increasing without snapback. When the avalanche-generated holes forward bias the body/source junction diode, NPN BJT is turned on to initiate snapback. Due to the turn-on operation of BJT inherent in the ggNMOS, the voltage across the ggNMOS is clamped down to the holding region. The maximum reverse diode current before the snapback of ggNMOS is defined as It1. For devices with large-array design, the effective device width (W) is usually higher than several thousands of micrometers in order to have high driving capability or low turn-on resistance in specified applications. With a large effective device width, considerable It1 can flow through large-array devices before the BJT triggers. Due to the area consideration, large array devices are not drawn with ESD design rules and non-uniform triggering among BJT inherent in the large-array device is serious. Consequently, triggering of BJT often induces devastating results to large-array devices [20]. Triggering of BJT has also been reported as the cause of ESD failures in HV power-rail ESD clamp circuits that utilize big field-effect transistors (BigFETs) [25].

Fig. 2.4. The typical I-V characteristic of a gate-grounded NMOS under ESD stresses.

For the 16-V nLDMOS, the heavily doped PBI reduces the effective resistance of P-Body (Rbody); It1 of nLDMOS is increased because turn on of BJT requires (It1  Rbody)  Vtdiode, where Vtdiode is the voltage to forward bias the P-Body/N+ junction diode. Due to the fact that considerable It1 can flow through large-array nLDMOS where BJT triggering is devastating, the additional P-type body implantation is beneficial to the ESD robustness of stand-alone large-array nLDMOS. ESD energy is mainly discharged through the reverse diode current (It1) of the large-array nLDMOS. However, without snapback to clamp down the voltage, large-array nLDMOS is not suitable to protect internal circuits.

For ESD protection nLDMOS devices that are not large-array devices, they usually rely on the turn-on operation of BJT to clamp down ESD voltages to their holding regions and to protect the gate oxide of internal circuits. They are therefore drawn with ESD design rules and the overall effective gate widths are much smaller compared to those of large-array nLDMOS devices. These devices exhibit low It1 because the high current density (It1/W) makes the P-Body/N+ diode easily forward biased under ESD stresses. As a result, the effect of PBI on increasing It1 is negligible. As shown in Fig. 2.3, both 16-V nLDMOS with and

without PBI implantation exhibit low It1 current. Furthermore, the magnitude of It1 is not critical for a non-large-array ESD protection nLDMOS. With the bipolar beta gain being suppressed, the measured It2 of nLDMOS was found to be degraded by PBI.

2.3. New Waffle Layout Structure for ESD Improvement

From the measurement results in Fig. 2.3, it is known that the PBI layer degrades ESD robustness of nLDMOS when the nLDMOS device relies on the parasitic BJT to discharge ESD energies. Because the available process modification from foundry is not effective in improving ESD robustness of snapback-based nLDMOS, a layout technique without additional mask or process step is proposed.

In low-voltage (LV) CMOS technologies, one of the most effective methods to increase ESD robustness is the substrate-triggered / substrate-pump technique [26]-[31]. To inject the substrate-triggered current into the base of the parasitic NPN BJT inherent in a LV NMOS, a P+ trigger node was placed at drain and connected to the trigger circuit [27]. However, in HV nLDMOS, the base of its parasitic NPN BJT is surrounded by the HV N-Well. The traditional layout method to inject the substrate-triggered current in LV technologies hence cannot be implemented in HV BCD processes.

To effectively inject the trigger current into the P-Body (the base of NPN BJT), nLDMOS realized in waffle layout style is proposed. Fig. 2.5(a) shows the layout diagram of nLDMOS with the waffle layout style (waffle nLDMOS). In the waffle nLDMOS, the drain of nLDMOS is drawn in a square. Source and body of the waffle nLDMOS are laid out at four sides of the drain square. Such a waffle layout style leads to four squares (Trigger Nodes) at the diagonal corner of a drain square. Both the P-Body regions in the two studied BCD processes are implanted before the formation of gate oxide; therefore the four squares at the diagonal corner of drain are shorted to the body pick up at source/body region. Device cross-sectional views along A-A’ and B-B’ lines of Fig. 2.5(a) are shown in Fig. 2.5(b) and

(a)

(b)

(c)

Fig. 2.5. (a) Layout top view, (b) device cross-sectional view along A-A’, and (c) device cross-sectional view along B-B’, of an nLDMOS with the proposed waffle layout style in the 0.5-m 16-V BCD process.

Source/

Body Drain

A

A’ B’ B

Trigger Node

2.5(c), respectively. By using the waffle layout, the body current can be injected from trigger nodes and be collected by the grounded P+ pick up at the source/body. The injected body current acts as the base current to turn on the parasitic NPN BJT. The P+ contacts at source/body in the waffle layout can ensure the grounded body potential during normal circuit operation. Trigger nodes of the waffle nLDMOS are dynamically biased through the circuit co-design method. A trigger circuit is designed to distinguish normal circuit operating and ESD stress conditions [6]. During normal circuit operating conditions, the trigger circuit biases the trigger nodes of the waffle nLDMOS at ground. During ESD stress conditions, the trigger circuit provides the required body injection current to enhance the turn-on uniformity of the waffle nLDMOS.

2.3.1. In the 0.5-m 16-V BCD Process

To verify the ability to turn on the parasitic NPN BJT, a stand-alone waffle nLDMOS with its trigger nodes connected to a bonding pad was injected with different levels of DC body current (IB) through its trigger nodes. Measurement setup is shown in the inset of Fig. 2.6, where the RBody denotes the equivalent resistance of P-Body from the trigger nodes to the P+

body pick-ups. With the larger injected IB current, the nLDMOS exhibited the higher collector current IC. This result shows the parasitic NPN BJT can be successfully triggered on through the body current injection.

To provide the body current during ESD stresses, a trigger circuit composed of a RC distinguisher and a HV inverter was fabricated on-chip. Because the ESD voltage transition has a rise time in the order of nanoseconds but normal circuit power-on transition is in the order of milliseconds, they can be distinguished through a proper design of the RC distinguisher. Corresponding measurement setup to verify the stand-alone trigger circuit is shown in the inset of Fig. 2.7. During the verification measurement, output of the stand-alone trigger circuit was externally short to the trigger nodes of a stand-alone 16-V waffle

nLDMOS. Fig. 2.7 shows that the trigger circuit can provide a peak trigger current (ITrigger) of 25 mA to the trigger nodes of the stand-alone waffle nLDMOS when a 20-V voltage pulse with 10-ns rise time (tr) and 1-s pulse width (tpw) was applied. After 200 ns, ITrigger fades to 0 mA because of the RC distinguisher.

Fig. 2.6. Turn-on verification of the stand-alone 16-V nLDMOS drawn in waffle style with DC body current (IB) injected from the trigger nodes.

Fig. 2.7. Turn-on verification of the stand-alone trigger circuit in the 0.5-m 16-V BCD process.

The measurement setup is shown in the inset of this figure.

Fig. 2.8. The 100-ns TLP-measured I-V curves of 16-V nLDMOS with stripe, waffle, and body-injected waffle layout style.

The 100-ns TLP-measured I-V curves among the stand-alone stripe, stand-alone waffle, and body-injected waffle nLDMOS devices are shown in Fig. 2.8. The stripe nLDMOS in Fig.

2.8 has the layout style of Fig. 2.1(a). The waffle nLDMOS in Fig. 2.8 has the layout style of Fig. 2.5(a), and the trigger nodes of the waffle nLDMOS are short to source internally. The body-injected waffle nLDMOS in Fig. 2.8 has the layout style as that shown in Fig. 2.5(a), and the trigger nodes in the body-injected waffle nLDMOS were connected internally to the trigger circuit through metal interconnection. The trigger circuit has the same design parameters to the one verified in Fig. 2.7. These three nLDMOS have the same device dimension of 363.6 m/0.35 m in layout. Failure criterion is the same to all devices, 1-A leakage current under 16-V drain bias voltage. Measured results show that the stripe and the waffle nLDMOS have roughly the same secondary breakdown current (It2) of 0.39 and 0.41 A, respectively, if the body current injection was not applied. By applying the body current injection, It2 of the waffle nLDMOS can be significantly increased from 0.41 to 0.95 A. From

the 100-ns TLP measurement, a more than 2X increase on It2 has been achieved through the waffle layout style and the body current injection. Measured HBM ESD robustness for stand-alone stripe, stand-alone waffle, and body-injected waffle nLDMOS devices are 0.75, 0.75, and 1.25 kV, respectively.

Fig. 2.9. Scanning electron microscope (SEM) image of the body-injected waffle nLDMOS after 100-ns TLP measurement.

Scanning electron microscope (SEM) image of the body-injected waffle nLDMOS after 100-ns TLP measurement is shown in Fig. 2.9. The failure location of the body-injected waffle nLDMOS was found on the drain of nLDMOS. This result shows that the ESD current is mainly discharged by the nLDMOS instead of the trigger circuit, and confirms the improvement on ESD robustness from the waffle layout and the body current injection.

2.3.2. In the 0.35-m 24-V BCD Process

In the 0.5-m 16-V BCD process, substantial improvement on the ESD robustness of nLDMOS has been achieved by using the waffle layout style along with the trigger circuit to provide body current injection. To study the width scaling to the ESD protection level of

nLDMOS, the circuit and layout co-design technique was fulfilled in a 0.35-m 24-V BCD process.

Fig. 2.10. TLP-measured I-V characteristics of stand-alone 24-V nLDMOS in stripe layout style.

Dimension for each finger of the stripe nLDMOS is 73.2 m/0.75 m.

Fig. 2.11. TLP-measured I-V characteristics of stand-alone 24-V nLDMOS in waffle layout style.

Dimension for each drain square of the waffle nLDMOS is 73.2 m/0.75 m.

(a)

(b)

Fig. 2.12. (a) SEM image of the stand-alone 24-V waffle nLDMOS with 22 drain squares after 100-ns TLP measurement and (b) the enlarged image of ESD the failure locations.

TLP-measured I-V characteristics of stand-alone stripe nLDMOS and stand-alone waffle nLDMOS in the 0.35-m 24-V BCD process are shown in Fig. 2.10 and 2.11, respectively.

The measured It2 for stand-alone stripe nLDMOS with 4, 6, 8, and 12 fingers are 1.94, 2.81, 3.15, and 3.16 A, respectively. Each finger of the 24-V stripe nLDMOS is 73.2 m/0.75 m.

For stand-alone waffle nLDMOS with 22, 33, and 44 drain squares, the measured It2 are 1.8, 2.78, and 3.49 A, respectively. Each drain square of the 24-V waffle nLDMOS is also

73.2 m/0.75 m. From the TLP measurement results, non-linear scaling of ESD robustness to the device width was observed on both stand-alone waffle and stand-alone stripe nLDMOS.

SEM image of the stand-alone 22 waffle nLDMOS after TLP measurement is shown in Fig.

2.12(a). ESD failures were found only on two drain squares of the 22 stand-alone waffle nLDMOS. Furthermore, the enlarged image of the ESD failure locations in Fig. 2.12(a) is shown in Fig. 2.12(b). Surface current filamentation are observed in Fig. 2.12(b), which implies a superficial current discharging of the stand-alone nLDMOS devices during ESD stresses.

In the 0.35-m 24-V BCD process, ESD detection circuit was also composed of a RC distinguisher and a HV inverter. A stand-alone trigger circuit was fabricated on-chip to verify the driving capability of the trigger circuit, as shown in Fig. 2.13. Corresponding measurement setup and device dimensions of the HV inverter are shown in the inset of Fig.

2.13. Output of the stand-alone trigger circuit was externally short to trigger nodes of a stand-alone waffle nLDMOS. A voltage pulse with 10-ns tr and 1-s tpw was given into the stand-alone trigger circuit. Measurement result showed a peak ITrigger of 50 mA into the trigger nodes of the waffle nLDMOS.

Fig. 2.13. Turn-on verification of the stand-alone trigger circuit in the 0.35-m 24-V BCD process.

The measurement setup is shown in the inset of this figure.

Fig. 2.14. TLP-measured I-V characteristics of body-injected 24-V nLDMOS with waffle layout style.

Fig. 2.15. Layout diagram of the 24-V stripe nLDMOS with additional P+ trigger bars at upper and bottom of the device for body current injection.

With the body current injection, TLP-measured I-V characteristics for body-injected waffle nLDMOS are shown in Fig. 2.14. TLP-measured It2 for body-injected waffle nLDMOS with 22, 33, and 44 drain squares are 2.07, 4.41, and 7.42 A, respectively. Besides the

body-injected waffle nLDMOS, the body current injection method was managed to be implemented on the nLDMOS with stripe layout style. As the layout diagram shown in Fig.

body-injected waffle nLDMOS, the body current injection method was managed to be implemented on the nLDMOS with stripe layout style. As the layout diagram shown in Fig.