Poly Bending Structure to SCR-nLDMOS

Despite a remarkably wider eSOA has been achieved by eliminating J1 and J2 currents through connecting GateSCR to ground, the J3 current still cause some degradation on eSOA performance especially under high gate biases. To further improve the eSOA and alleviate the degradation due to J3, a new poly bending (PB) layout structure for SCR-nLDMOS arrays

(PB-SCR-nLDMOS) has been proposed. For all studied PB-SCR-nLDMOS, DP width was kept at 50 m and devices were drawn with PBI layer.

(a)

(b)

Fig. 4.9. (a) Layout top view and (b) cross-sectional view along D-D’ line of SCR-nLDMOS with the proposed poly bending structure. Widths and spacings in figures are not drawn to scale.

In the poly bending layout, GateSCR has been modified from a straight poly line from top to bottom of drain regions to part of a straight poly line in parallel with N+ drain but several

trapezoids in parallel with P+ drain, as the layout top view of a PB-SCR-nLDMOS shown in Fig. 4.9(a). By bending the poly gate in layout, additional P+ diffusion regions filling trapezoids can be inserted at source side. Each trapezoid region was drawn with one contact (ground dot) connecting to source/body. The bottom length of every trapezoids is 2.66 m (top edge of P+ to bottom edge of P+), and the pitch between two adjacent ground dots is defined as S in the layout of Fig. 4.9(a).

Device cross-sectional view along D-D’ line in Fig. 4.9(a) is shown in Fig. 4.9(b). When the emitting holes from P+ anode are swept toward the ground potential (the J3 current flow), most of the emitting holes are collected by the ground dot because its parasitic resistance RPB

is smaller than the parasitic resistance RX from P-body/PBI to the P+ body contact, as shown in Fig. 4.9(b). Moreover, holes collected by the ground dots do not build up the voltage underneath N+ source, i.e. do not help forward bias the base-emitter junction of NPN BJT.

Accordingly, only a small part of J3 that is not collected by the ground dot can help trigger embedded SCR, which, in turn, substantially alleviates the degradation on eSOA due to the J3

current flow.

Measured eSOA for PB-SCR-nLDMOS arrays are shown in Fig. 4.10. For comparison, the measured eSOA of ggSCR-nLDMOS with DP of 50 m in Fig. 4.8 is also included in Fig.

4.10 and labeled as ggSCR-nLDMOS. In Fig. 4.10, PB structures that have GateSCR

connected to GateMOS show narrower eSOA boundaries compared to that of ggSCR-nLDMOS when S are 10 and 15 m. When S is reduced to 5 m, PB structure (with GateSCR connected to GateMOS) shows a better eSOA performance than that of ggSCR-nLDMOS in Fig. 4.10. In the studied PB structures, because the bottom length of a trapezoid is 2.66 m, S of 15 m indicates that there is a 12.34-m long straight poly line between two ground dots to induce J1 and J2 currents and to further trigger on the embedded SCR when GateSCR is connected to GateMOS. When S is larger than 5 m, J1 and J2 currents dominate the triggering mechanism of embedded SCR, so that measurement results for PB

with S of 10 and 15 m are inferior to ggSCR-nLDMOS in Fig. 4.10. However, by comparing the eSOA of SCR-nLDMOS with 50-m DP and PBI in Fig. 4.6, and the eSOA of PB-SCR-nLDMOS with S of 10 and 15 m in Fig. 4.10, improvement on eSOA by using the poly bending layout structure is still noticeable. This result comes from the fact that the ground dots introduce another parasitic resistor RPB in parallel with the RX resistor in Fig. 4.4, which widens the eSOA boundary by making base-emitter junction of parasitic NPN BJT harder to be forward biased. When S is reduced to 5 m, the straight poly line between two adjacent ground dots which can induce J1 and J2 currents is greatly reduced to 2.34 m. Note that there is no channel current flowing widthwise along the trapezoidal regions because of the P+ region in ground dots to cut off electron current flow (Fig. 4.9(b)). A better eSOA performance is therefore observed when S is reduced to 5 m.

Fig. 4.10. Performance of poly bending structure on eSOA of SCR-nLDMOS. The “PB” devices have poly bending structure with GateSCR internally connected to GateMOS. The “PB & gg” devices have poly bending structure with Gate_SCR internally connected to source/body. The corresponding gate biases for the I_DS from low to high were 0, 3, 6, 9, 12, and 16 V, respectively.

When GateSCR is connected to source/body to rule out the effects from J1 and J2, effectiveness of the poly bending structure on suppressing J3 starts to manifest clearly.

Substantially widened eSOA boundaries, especially under high gate biases, have been observed from the measurement results in Fig. 4.10 (PB & gg devices). Measured VDS ratings for PB & gg devices in Fig. 4.10 under 16-V gate bias are 30.81, 31.52, and 33.67 V for S of 15, 10, and 5 m, respectively. In summary, grounding GateSCR fingers not only blocks J1 and J2 currents, but also benefits from the reduced surface field (RESURF) effect of poly field plate in GateSCR fingers. The additional P+ ground dots in poly bending structure further reduce the bipolar beta gain and lower the base resistance of parasitic NPN BJTs. With above reasons, the eSOA of SCR-nLDMOS can be greatly improved by using the poly bending layout structure with grounded GateSCR fingers.

Fig. 4.11. Measured TLP I-V characteristics of poly bending SCR-nLDMOS with different S spacings. Gate bias for all DUTs was 0 V and the leakage currents were monitored under 24-V drain bias.

TLP-measured I-V characteristics for PB-SCR-nLDMOS with DP of 50 m are shown in Fig. 4.11. All measured devices in Fig. 4.11 have It2 higher than the equipment limitation of 3.75 A. Measured holding voltages (Vh) for PB-SCR-nLDMOS with S of 15, 10, and 5 m in

Fig. 4.11 are 3.99, 4.26, and 5.67 V, respectively. Measured Vh for SCR-nLDMOS with DP of 50 m in Fig. 4.5(b) is 2.14 V. Accordingly, from the viewpoint of power dissipation during ESD stresses, poly bending structure is expected to have some negative impact on the ESD robustness. However, because the measured HBM ESD robustness for all DUTs in Fig. 4.11 is higher than 8 kV, the PB-SCR-nLDMOS arrays are still extremely robust against ESD stresses.

4.5. Summary

In HV technologies, output arrays with embedded SCR are usually adopted for on-chip ESD protection. However, a substantially narrowed eSOA has been found due to the insertion of SCR into HV nLDMOS. Embedding SCR therefore may jeopardize the reliability of output arrays during normal circuit operating conditions, even though it provides a superior ESD robustness to protect output array. Experimental results showed that SCR insertion with small but multiple P+ segments can help alleviate the degradation on eSOA. By grounding the gates of fingers in the embedded SCR, eSOA can be substantially widened. But, drifting electrons due to carrier multiplication process from adjacent conducting fingers can still result in a roll off on the maximum VDS rating, especially under high gate bias conditions.

Through the proposed poly bending structure, impact from these drifting electrons can be mitigated and a further widened eSOA has been achieved. With the high ESD robustness and greatly widened eSOA boundaries shown in this chapter, the poly bending layout structure with a proper gate connection has been verified as a promising design technique to enhance reliability of high voltage output arrays with embedded SCR.

Chapter 5

New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully-Silicided CMOS Processes

5.1. Background

To increase the driving capability and the maximum operating frequencies of MOSFETs, silicidation has been widely adopted in chip fabrications since deep-submicron CMOS era. In the fully-silicided CMOS technologies, the silicidation is typically carried out through metallurgical reaction between silicon and the pre-deposited silicide metal (Titanium, Cobalt, or Nickel) [82]–[85]. With proper annealing steps, refractory metal silicides are formed to provide a low resistivity for the diffusions and poly silicon gates of MOSFETs.

Although the low resistivity from silicides is advantageous to the driving capability and operating frequencies of MOSFETs, it has been reported that silicidation induces electrostatic discharge (ESD) degradation due to the current crowding within a shallow surface [86].

Moreover, the bend-down of silicidation located near the shallow trench isolation (STI) corner leads to deterioration of ESD robustness of fully-silicided devices [87]. Owing to these effects during ESD stresses, silicidation has been confirmed to result in precipitous degradation on ESD protection levels of CMOS ICs in advanced CMOS technologies.

To recover the silicidation-induced degradation on ESD robustness, CMOS processes with additional silicide blocking (SB) has been proposed [88]–[94]. Because the temperature for silicon dioxide (SiO2) to form metallurgical silicides is higher than that for silicon, SB can be achieved by depositing sacrificial oxide on the selected regions before the deposition of silicide metal. The sacrificial oxide therefore separates the contact between silicon and the silicide metal, preventing these selected regions from silicidation during the subsequent

annealing processes. By using the SB on ESD protection devices, ESD robustness of CMOS ICs can be restored without affecting the operating speed of internal circuits. However, to deposit the sacrificial oxide and to define the selected regions for silicide blocking, additional mask and process steps are required. As a result, introducing SB into the CMOS manufacturing processes will increase the fabrication cost. To compromise with the fabrication cost, or owing to the inaccessibility of SB in some given process technologies, some cost-effective ballasting techniques have been proposed to improve ESD robustness of fully-silicided MOSFETs [95]–[108].

The mechanism and previous works of ballasting techniques on fully-silicided MOSFETs are briefly reviewed in this chapter. Two new ballasting layout schemes are proposed to effectively improve ESD robustness of I/O buffers with fully-silicided NMOS and PMOS transistors. Experimental results from real IC products fabricated in a 0.35-m fully-silicided CMOS process have confirmed that the new ballasting layout schemes can successfully increase HBM ESD robustness of fully-silicided I/O buffers from the original 1.5 to over 6 kV without using the additional silicide-blocking mask. Moreover, by using the new proposed ballasting layout schemes, no additional layout area of I/O buffers is required, compared to that drawn with the traditional silicide-blocking technique [97].

5.2. Review on Ballasting Techniques for Fully-Silicided I/O Buffers

Due to the huge discharging current in ESD events, current crowding has been known to cause serious impact on ESD protection devices. By increasing the ballast resistance in the ESD protection MOSFETs, ESD current path can be spread deeper into the substrate of large volume, which in turn improves ESD robustness [86]. Moreover, sufficient ballast resistance can improve the turn-on uniformity of ESD protection NMOS with multi-fingers in layout.

Fig. 5.1. Current-voltage (I-V) characteristics of gate-grounded NMOS for ESD protection, indicating the relation between Vt2 and Vt1 values to the uniform or non-uniform triggering.

In a multi-finger NMOS, different distances from the drain region of each finger to the grounded guard ring result in asymmetry of substrate resistance, which causes the central fingers of NMOS to be more easily triggered on under ESD stresses [26]. After the triggering of the multi-finger NMOS under ESD stresses, the ESD overstress voltage is clamped to its holding voltage (Vh) plus the product of ESD current (IESD) and the turn-on resistance (Ron).

The typical I-V curve of gate-grounded NMOS under ESD stress is illustrated in Fig. 5.1.

Without sufficient ballast resistance, (IESD × Ron) is not large enough to make the secondary breakdown voltage (Vt2) higher than the trigger voltage (Vt1). As a result, ESD current is concentrated in some earlier turned-on area to cause local damages but the rest area cannot be triggered on in time to discharge ESD current. Such non-uniform turn-on behavior among the multiple fingers of NMOS limits its ESD robustness, even if the NMOS was drawn with a large device dimension. By introducing the ballast resistance Rballast, turn-on resistance of the multi-finger NMOS can be increased from Ron to (Ron + Rballast). As long as the Vt2’ can be increased greater than Vt1, the multi-finger NMOS can be uniformly triggered on during ESD

stresses [109]. As a result, sufficient ballast resistance can force ESD current being conducted into the deeper substrate, and also increase the ESD robustness due to the improvement of turn-on uniformity among the multiple fingers of gate-grounded NMOS.

To realize the ballast resistance in fully-silicided NMOS, one of the layout methods is to use the high sheet resistance from N-Well. Fig. 5.2 shows the device cross-sectional view of an NMOS with the N-Well ballasting technique. The ballast N-Well electrically shorts the separated diffusions and contributes the desired Rballast to the overall turn-on resistance of NMOS [95]–[97]. The holding voltage and the trigger voltage of NMOS may be also increased due to the insertion of ballast N-Well. For the facility of description, the separated diffusion that connects to the input/output (I/O) pad is labeled as the island diffusion in this chapter. The other separated diffusion, which is closer to the gate of MOSFET, is labeled as the drain diffusion. Isolation in figures of this chapter represents either field oxide (FOX) or STI.

Fig. 5.2. Ballast N-Well to increase the ballast resistance of NMOS. The separated diffusion region that connects to I/O Pad is labeled as island diffusion, and the diffusion region that closer to the gate is labeled as drain diffusion.

Although the ballast N-Well is useful to increase ESD robustness of fully-silicided NMOS, it makes layout area to expand due to the process ability of defining the minimum spacing between two adjacent diffusion regions. Generally, technology nodes with isolation of local oxidation of silicon (LOCOS) ask for larger spacing for two adjacent diffusion regions than those with STI isolation because of the bird’s beak encroachment during wet oxidation [110].

With the finest process controllability over the gate length in CMOS technologies, replacing the separation between island and drain diffusions from FOX (or STI) to dummy poly gate minimizes the spacing between two adjacent diffusion regions [98], [99]. Although the N-Well ballasting technique is useful and easy to be utilized on fully-silicided NMOS, it cannot be applied to fully-silicided PMOS which is implemented in the N-Well.

In CMOS technologies, the resistance from a single contact, via, or interconnects keeps increasing due to the constant shrinkage on either horizontal or vertical dimensions [111]. As a result, some ballasting techniques with back-end elements were used to build up the ballast resistance without increasing the process complexity [100]–[104]. By stacking as many metal layers as possible to construct a vertically meandering ESD current path, the back-end-ballast (BEB) technique is simple to increase the ballast resistance in the ESD protection MOSFETs.

Poly BEB and contact ballasting (CTB) techniques further segment the current conduction path into several parallel branches, and insert polysilicon or diffusion resistors in series with every back-end segmentation to facilitate the ballast of BEB technique [100]–[103]. When a local segment starts to suffer current crowding, the poly or diffusion resistor on the segment induces current defocus feedback, which forces ESD current to redistribute and hence improves the turn-on uniformity during ESD stresses [100], [104].

(a)

(b)

Fig. 5.3. The (a) layout top view and (b) device cross-sectional view along A-A’ line of the fully-silicided NMOS with floating poly array (FPA) technique [107].

To further shrink the layout area of the fully-silicided MOSFETs due to the additional polysilicon resistor in the poly BEB technique, the active-area-segmentation (AAS) technique has been proposed [104]. In the AAS technique, source or drain regions are segmented to diffusion stripes to ballasts the MOSFET for ESD protection with current defocus feedback.

Moreover, the AAS technique holds the potential of featuring extremely compact layout area.

The bulk coupling effect therefore alleviates the non-uniform triggering and increases the ESD robustness of MOSFETs [112]. Effectiveness of the bulk coupling effect has been confirmed by floating the body of NMOS under ESD stresses [113].

Besides, some ballasting methods manage to increase the ballast resistance by creating a horizontally meandering current path on diffusion regions, such as the staggered diffusion technique [106] and the floating poly array (FPA) technique [107]. As the layout top view of FPA technique shown in Fig. 5.3(a), the interlaced floating poly array intervenes in the straightforward current path along A-A’. The current flow path is therefore forced to wind within the FPA as indicated in Fig. 5.3(b), which increases the equivalent ballast resistance to improve ESD robustness.

From the previous works, sufficient ballast resistance drives ESD current deeper into substrate to gain better heat dissipation. The ballast resistance contributes to the overall turn-on resistance, which fulfills the (Vt2 > Vt1) condition to enhance the turn-on uniformity of NMOS under ESD stresses. Even in the condition of (Vt2 < Vt1), current defocus feedback and bulk coupling effect can still prevent MOSFETs from being easily filamented during ESD events.

5.3. Fully-Silicided I/O Buffers under ESD Stresses

Because there are four ESD test modes at an I/O pad, both the NMOS and the PMOS in an I/O buffer are susceptible to ESD failure. For example, the PS-mode ESD tests can lead to breakdown of the driver NMOS whereas the ND-mode ESD tests can lead to breakdown of the driver PMOS. Though the whole-chip ESD protection scheme equipped with power rail ESD clamp circuit is effective to discharge ESD energy by avoiding junction breakdown of I/O buffers [6], the overshooting or undershooting voltage are still harmful to the I/O buffer, especially under the conditions with high ESD stress voltage.

In this section, effectiveness of the N-Well ballasting technique to whole-chip ESD

robustness of fully-silicided I/O buffers is investigated. Chips are fabricated in a 0.35-m 5-V fully-silicided CMOS process with LOCOS isolation. Silicide blocking is not available in this process due to the consideration of cost reduction. Because the N-Well ballasting technique cannot be applied to PMOS, the driver PMOS in the I/O buffer discussed in this section was left un-ballasted. All I/O buffers are self-protected, which have no additional ESD protection device connected to the I/O pad. The whole-chip ESD protection scheme with the corresponding device dimensions are illustrated in Fig. 5.4. Operating frequency specification of the I/O buffers is 20 MHz. The main ESD protection NMOS (MN2) in the active power-rail ESD clamp circuit has a total device dimension (W/L) of 1680 m/1.25 m. For fully-silicided I/O buffers without ballasting, no ballasting technique was applied to MN2 of the power-rail ESD clamp circuit. With the proposed layout schemes, the N-Well ballasting technique was also applied to MN2 of the power-rail ESD clamp circuit when the N-Well ballasting technique was applied in the I/O buffers.

Fig. 5.4. Whole-chip ESD protection scheme and the corresponding device dimensions of the power-rail ESD clamp circuit.

Target for ESD robustness of those IC products requested by customers is to pass 6-kV HBM ESD test. To verify ESD robustness, the starting voltage of HBM ESD test is 0.5 kV, and the step voltage during ESD tests is 0.5 kV. Each pin is stressed three times with the specified HBM ESD level and the failure criterion is an over 20% I-V shift compared to the original I-V curve before ESD stress. The test will stop when ESD failure happens on one or more I/O (including power) pin(s).

Fig. 5.5. Layout top view of the self-protected fully-silicided I/O buffer in a CMOS IC product.

5.3.1. Fully-Silicided I/O Buffer Without Ballasting

In nowadays CMOS ICs, to minimize the required layout area for I/O buffers, self-protected I/O design (I/O buffer without additional ESD protection devices) is usually adopted. Layout of the self-protected I/O buffers in a CMOS IC product is shown in Fig. 5.5.

Gate length in the I/O buffer is increased to avoid the reverse channel length dependency

Gate length in the I/O buffer is increased to avoid the reverse channel length dependency