Review on Ballasting Techniques for Fully-Silicided I/O Buffers

Due to the huge discharging current in ESD events, current crowding has been known to cause serious impact on ESD protection devices. By increasing the ballast resistance in the ESD protection MOSFETs, ESD current path can be spread deeper into the substrate of large volume, which in turn improves ESD robustness [86]. Moreover, sufficient ballast resistance can improve the turn-on uniformity of ESD protection NMOS with multi-fingers in layout.

Fig. 5.1. Current-voltage (I-V) characteristics of gate-grounded NMOS for ESD protection, indicating the relation between Vt2 and Vt1 values to the uniform or non-uniform triggering.

In a multi-finger NMOS, different distances from the drain region of each finger to the grounded guard ring result in asymmetry of substrate resistance, which causes the central fingers of NMOS to be more easily triggered on under ESD stresses [26]. After the triggering of the multi-finger NMOS under ESD stresses, the ESD overstress voltage is clamped to its holding voltage (Vh) plus the product of ESD current (IESD) and the turn-on resistance (Ron).

The typical I-V curve of gate-grounded NMOS under ESD stress is illustrated in Fig. 5.1.

Without sufficient ballast resistance, (IESD × Ron) is not large enough to make the secondary breakdown voltage (Vt2) higher than the trigger voltage (Vt1). As a result, ESD current is concentrated in some earlier turned-on area to cause local damages but the rest area cannot be triggered on in time to discharge ESD current. Such non-uniform turn-on behavior among the multiple fingers of NMOS limits its ESD robustness, even if the NMOS was drawn with a large device dimension. By introducing the ballast resistance Rballast, turn-on resistance of the multi-finger NMOS can be increased from Ron to (Ron + Rballast). As long as the Vt2’ can be increased greater than Vt1, the multi-finger NMOS can be uniformly triggered on during ESD

stresses [109]. As a result, sufficient ballast resistance can force ESD current being conducted into the deeper substrate, and also increase the ESD robustness due to the improvement of turn-on uniformity among the multiple fingers of gate-grounded NMOS.

To realize the ballast resistance in fully-silicided NMOS, one of the layout methods is to use the high sheet resistance from N-Well. Fig. 5.2 shows the device cross-sectional view of an NMOS with the N-Well ballasting technique. The ballast N-Well electrically shorts the separated diffusions and contributes the desired Rballast to the overall turn-on resistance of NMOS [95]–[97]. The holding voltage and the trigger voltage of NMOS may be also increased due to the insertion of ballast N-Well. For the facility of description, the separated diffusion that connects to the input/output (I/O) pad is labeled as the island diffusion in this chapter. The other separated diffusion, which is closer to the gate of MOSFET, is labeled as the drain diffusion. Isolation in figures of this chapter represents either field oxide (FOX) or STI.

Fig. 5.2. Ballast N-Well to increase the ballast resistance of NMOS. The separated diffusion region that connects to I/O Pad is labeled as island diffusion, and the diffusion region that closer to the gate is labeled as drain diffusion.

Although the ballast N-Well is useful to increase ESD robustness of fully-silicided NMOS, it makes layout area to expand due to the process ability of defining the minimum spacing between two adjacent diffusion regions. Generally, technology nodes with isolation of local oxidation of silicon (LOCOS) ask for larger spacing for two adjacent diffusion regions than those with STI isolation because of the bird’s beak encroachment during wet oxidation [110].

With the finest process controllability over the gate length in CMOS technologies, replacing the separation between island and drain diffusions from FOX (or STI) to dummy poly gate minimizes the spacing between two adjacent diffusion regions [98], [99]. Although the N-Well ballasting technique is useful and easy to be utilized on fully-silicided NMOS, it cannot be applied to fully-silicided PMOS which is implemented in the N-Well.

In CMOS technologies, the resistance from a single contact, via, or interconnects keeps increasing due to the constant shrinkage on either horizontal or vertical dimensions [111]. As a result, some ballasting techniques with back-end elements were used to build up the ballast resistance without increasing the process complexity [100]–[104]. By stacking as many metal layers as possible to construct a vertically meandering ESD current path, the back-end-ballast (BEB) technique is simple to increase the ballast resistance in the ESD protection MOSFETs.

Poly BEB and contact ballasting (CTB) techniques further segment the current conduction path into several parallel branches, and insert polysilicon or diffusion resistors in series with every back-end segmentation to facilitate the ballast of BEB technique [100]–[103]. When a local segment starts to suffer current crowding, the poly or diffusion resistor on the segment induces current defocus feedback, which forces ESD current to redistribute and hence improves the turn-on uniformity during ESD stresses [100], [104].

(a)

(b)

Fig. 5.3. The (a) layout top view and (b) device cross-sectional view along A-A’ line of the fully-silicided NMOS with floating poly array (FPA) technique [107].

To further shrink the layout area of the fully-silicided MOSFETs due to the additional polysilicon resistor in the poly BEB technique, the active-area-segmentation (AAS) technique has been proposed [104]. In the AAS technique, source or drain regions are segmented to diffusion stripes to ballasts the MOSFET for ESD protection with current defocus feedback.

Moreover, the AAS technique holds the potential of featuring extremely compact layout area.

The bulk coupling effect therefore alleviates the non-uniform triggering and increases the ESD robustness of MOSFETs [112]. Effectiveness of the bulk coupling effect has been confirmed by floating the body of NMOS under ESD stresses [113].

Besides, some ballasting methods manage to increase the ballast resistance by creating a horizontally meandering current path on diffusion regions, such as the staggered diffusion technique [106] and the floating poly array (FPA) technique [107]. As the layout top view of FPA technique shown in Fig. 5.3(a), the interlaced floating poly array intervenes in the straightforward current path along A-A’. The current flow path is therefore forced to wind within the FPA as indicated in Fig. 5.3(b), which increases the equivalent ballast resistance to improve ESD robustness.

From the previous works, sufficient ballast resistance drives ESD current deeper into substrate to gain better heat dissipation. The ballast resistance contributes to the overall turn-on resistance, which fulfills the (Vt2 > Vt1) condition to enhance the turn-on uniformity of NMOS under ESD stresses. Even in the condition of (Vt2 < Vt1), current defocus feedback and bulk coupling effect can still prevent MOSFETs from being easily filamented during ESD events.