I/O Buffer with The New Proposed Layout Scheme (Type A)

To provide efficient ballast on the driver PMOS, Fig. 5.9 shows the diagram of type-A layout scheme. The driver NMOS in the type-A layout scheme is drawn with N-Well ballasting. However, the drain of the driver PMOS is not connected directly to the I/O pad.

Instead, drain of the PMOS is connected to the drain diffusion of the driver NMOS, which is electrically connected to the I/O pad by means of the ballast N-Well. The driver NMOS and PMOS in the type-A layout scheme have the same device dimensions as those in the I/O buffers with N-Well ballasting technique on driver NMOS. The main ESD protection NMOS (MN2) of the power-rail ESD clamp circuit in this scheme is N-Well ballasted. Device cross-sectional view along A-A’ in Fig. 5.9 is shown in Fig. 5.10. It can be understood from Fig. 5.10 that only the island diffusion of the driver NMOS is directly connected to the I/O pad. Through such a layout arrangement, PMOS current is forced to flow through the N-Well ballast resistor in the driver NMOS, enforcing the N-Well to ballast both driver NMOS and PMOS during ESD stresses.

In the type-A layout scheme, the ESD current under PS-mode ESD tests first flows to the floating VDD through the N-Well ballast resistor and the DP diode. Then, the ESD current is discharged to the grounded VSS through the power-rail ESD clamp circuit. Under the PD-mode ESD tests, the ESD current is first discharged to the grounded VDD through the N-Well ballast resistor and the DP diode. Therefore, voltages across the stressed I/O pad and

ground under the PS- and PD- mode ESD tests are

ΔVPS = [IESD × (Rballast + Ron, DP + RVDD + Ron, Power-Rail) + Vt, DP] (5.2) and

ΔVPD = [IESD × (Rballast + Ron, DP + RVDD) + Vt, DP] . (5.3)

Fig. 5.11. TLP-measured I-V curves for the I/O buffer with the type-A layout scheme. The tests were manually stopped at 2 A without causing failure to the I/O buffer.

With the ESD current being forced to flow through the N-Well under PS- and PD- mode conditions, it has been reported that the N-Well resistor under high current level exhibits high resistance characteristic due to drift velocity saturation [97]. As the TLP measurement results shown in Fig. 5.11, under PS-mode (positive TLP stress on I/O pad with VSS relatively grounded) and PD-mode (positive TLP stress on I/O pad with VDD relatively grounded) TLP measurements, the drift velocity saturation results in the 24-V voltage at IESD of 0.5 A. The applied voltage is mainly dropped within the N-Well region. At the same time, electron-hole pairs are generated to support the increased current, and electric field is built up toward the N+ island diffusion/N-Well junction. The electric field build-up eventually results in

avalanche breakdown to happen at the N+/N-Well junction, which results in the snapback as observed in Fig. 5.11. With the avalanche breakdown at N+/N-Well junction, the hole concentration can exceed the background doping of N-Well, and results in conductivity modulation to lower the turn-on resistance of N-Well [116], [117]. For NS-mode (positive TLP stress on VSS pin with I/O pin relatively grounded) and ND-mode (positive TLP stress on VDD pin with I/O pin relatively grounded) TLP measurements, ESD currents are discharged through the DN diode and the power-rail ESD clamp circuit (in ND-mode test) without flowing through the ballast N-Well. Therefore, the high resistance characteristic from N-Well is not observed in the ND- and NS- mode TLP I-V curves in Fig. 5.11.

Fig. 5.12. SEM image of the fully-silicided I/O buffer realized with the type-A layout scheme after 6.5-kV PS-mode ESD stress. Uniformly distributed N+-to-N-Well ESD damages are found on the driver NMOS.

HBM ESD measurement results in Table 5.1 show that the fully-silicided I/O buffers with the type-A layout scheme have the PS- and PD-mode ESD protection levels as high as 6 kV.

Under the ND-mode ESD tests, though the ΔVND can exceed Vt1 of the driver PMOS under

high ESD stress voltage, the N-Well ballast resistor suppresses the ESD current discharged through the PMOS. Accordingly, fully-silicided I/O buffers with type-A layout scheme have ND-mode HBM ESD robustness over 8 kV. By using the type-A layout scheme, ND-mode ESD failure on the driver PMOS has been successfully overcome and the 6-kV performance target has been achieved.

Among the four ESD test modes on I/O buffers, ESD current under PS- and PD-mode ESD tests has to flow through the ballast N-Well. The N+/N-Well junction breakdown is expected to result in large power dissipation over the ballast N-Well, which results contact spiking on island diffusions of the driver NMOS. With the ESD current flowing from island diffusion through the ballast N-Well to the drain diffusion of driver NMOS, melted metal contacts can result in a short from island diffusion to the drain diffusion of driver NMOS, which results in substantial shift of I-V curve compared to the original I-V curve before ESD stress. The I/O buffer is then judged as a failure because short of island and drain diffusions results in I-V shift over 20% compared to the original I-V curve before ESD stress. The melted metal contacts may also result in a short from island diffusion to the P-Substrate, which can also cause sharp I-V shift after ESD stress. Consequently, the N+-to-N-Well ESD failure has become the limitation to the type-A layout scheme. As the SEM image shown in Fig. 5.12, the I/O buffer after 6.5-kV PS-mode ESD stress shows N+-to-N-Well failure on the driver NMOS. From the uniformly distributed ESD failure locations in Fig. 5.12, the effectiveness of the type-A layout scheme to ballast the I/O buffer for ESD protection has been verified.