7. Investigation on The Transistor Holding Voltage Acquired from TLP in
7.3. Experimental Results and Discussion
The I-V characteristic of the nLDMOS under 100-ns TLP measurement is shown in Fig.
7.2(a) (squares). Steps of the T-line pre-charge voltage are 0.5 V, and I-V points are the averaged data from 50% to 90% of the pulse period. It2 of the nLDMOS is 1.5 A, and the corresponding HBM ESD robustness is higher than the general requirement of 2 kV. From the 100-ns TLP measurement, the nLDMOS shows a holding voltage of 11 V. However,
distinct from the results of low voltage devices, the holding voltage of nLDMOS under curve tracer measurement shows a substantial inconsistency to that measured by 100-ns TLP. As shown in Fig. 7.2(b), the holding voltage of nLDMOS under curve tracer measurement is 5.7 V only.
(a)
(b)
Fig. 7.2. I-V characteristics of the nLDMOS measured by (a) 100-ns and 1000-ns TLP, and (b) a DC curve tracer.
To investigate the huge Vh roll off from 100-ns TLP (11 V) to curve tracer (5.7 V), long-pulse TLP system with 1000-ns pulse width [134] was exploited. The long-pulse TLP
system is capable of providing pulse widths longer than100ns, so that the time-domain device behavior of HV devices after 100ns can be further observed. As the measured result shown in Fig. 7.2(a) (solid triangles), nLDMOS under 1000-ns TLP has Vh of 9.1 V, which is lower than the Vh under 100-ns TLP measurement but higher than the Vh under curve tracer measurement. The corresponding time-domain current and voltage waveforms of 1000-ns TLP measurement are shown in Fig. 7.3, where perceptible degradation over time is observed.
Fig. 7.3. Time-domain waveforms of the nLDMOS under 1000-ns long-pulse TLP measurement.
From the Wunsch-Bell model, the simplified temperature model T(0, ) under the power source of a rectangular pulse with duration is (0, ) q0
T t
D
(t ) [135]. As a result, device temperature increases with time (t ) during the duration of TLP pulses ( ). In HV devices, the high device holding voltages can further accelerate the self-heating effect.
With the increasing device temperature over time, -gain of the parasitic bipolar inherent in nLDMOS also increases. The holding voltage of nLDMOS therefore degrades while the time increases, as the waveform shown in Fig. 7.3. Extrapolating the measured voltage waveform in Fig. 7.3, time for the nLDMOS to reach Vh of 5.7 V is estimated as 3.2 s.
Fig. 7.4. Time-domain voltage waveform of the nLDMOS under transient latchup measurement with initial positive Vcharge of +30V.
Transient latchup test has been verified as an effective test method to evaluate the susceptibility of CMOS ICs to the latchup induced by transient noises in field applications [136]–[138]. The test setup for TLU is shown in the inset of Fig. 7.4. In the TLU test, the nLDMOS was initially biased at normal circuit operating voltage of 18 V. A transient noise is injected into nLDMOS from the transient trigger source with pre-charged voltage Vcharge of +30 V. After the transient triggering, the nLDMOS was driven into latchup state and clamped down the supply voltage. From the measured voltage waveform of TLU test in Fig. 7.4, the nLDMOS clamped the supply voltage to ~5.7 V, which is the same value of Vh under curve-tracer measurement. Moreover, time for nLDMOS to clamp the supply voltage into a steady state is roughly around 1000 ns, whereas the voltage at 1000 ns under 1000-ns TLP measurement in Fig. 7.3 is ~9 V. In consequence, the TLU test has verified that the TLP system overestimates the holding voltage of a HV device, which, in turn, could underestimate its susceptibility to latchup.
7.4. Summary
The holding voltage of an nLDMOS in a HV BCD process has been investigated by TLP measurements with different pulse widths and DC curve tracer. It is found that the holding voltages of an 18-V nLDMOS measured by 100-ns TLP system and curve tracer are substantially different, 11 and 5.7 V , respectively. The self-heating effect which degrades the holding voltage of nLDMOS over time has been observed. By using the long-pulse TLP, the self-heating speed of the HV transistors can be quantitatively estimated. TLU test further verifies that TLP systems overestimate the holding voltage of nLDMOS and underestimate its susceptibility to latchup. As a result, TLP measurement is not suitable for investigating the holding voltage of HV devices, especially for the latchup development because latchup events have the time duration longer than a millisecond.
Chapter 8
Conclusions and Future Works
This chapter summarizes main results of this dissertation and from the research results some suggestions and future works are proposed.
8.1. Main Results of This Dissertation
After a brief ESD introduction in Chapter 1, a waffle layout method that utilizes the body-current injection on the nLDMOS is proposed in Chapter 2. Through TLP and ESD measurements and failure analyzes, experimental results show that this proposed method is able to substantially improve turn-on uniformity of nLDMOS transistors in a 0.5-m 16-V and a 0.35-m 24-V BCD process. This waffle layout structure is suitable for I/O or power-rail ESD clamp circuit.
For open-drain structures, integrating SCR into output nLDMOS is a common ESD solution. However, the safe operating area, as one of the important reliability indicators of output arrays, is degraded due to the embedded SCR. In Chapter 3, SOA is reviewed along with some up-to-date technologies on improving SOA of HV transistors. Following the SOA review in Chapter 3, a poly bending method that alleviates the degradation on SOA performance but keeps the high ESD robustness from SCR is proposed in Chapter 4. With the poly bending layout method, a HV output array that has both high ESD robustness and wide SOA is available for HV ICs. Combining the results in Chapter 2 and 4, the two methods can provide excellent ESD robustness to HV ICs with either traditional or open-drain structures.
With ESD being a practical reliability requirement of ICs, two ESD designs for fully-silicided technologies are included in Chapter 5 and Chapter 6. In Chapter 5, two novel ballasting techniques are proposed. The proposed methods ballast not only the output NMOS,
but also the output PMOS transistor to maximize the ESD robustness. From measurement results on a real IC product, the two ballasting method effectively equipped the IC with at least 6 kV HBM ESD robustness.
In chapter 6, a fully-silicided ESD protection design for voltage programming pins is proposed. The proposed design features both high ESD protection level and high immunity against mis-triggering when the input voltage has a rise time similar to ESD events, tens of nanoseconds. A commercial IC equipped with this ESD protection circuit passed 5-kV HBM ESD robustness. Finally, in Chapter 7, a new phenomenon of HV transistors’ holding voltage in response to stress time is investigated by using TLP systems with different pulse widths.
Results in Chapter 7 are useful for the future development of high-latchup-immunity transistors or ICs in HV technologies.
8.2. Future works
For the operation of power MOSFETs, it is very often that the transistors’ drain or ground potentials be perturbed greatly, especially when switching with a large current. Noise immunity of the nLDMOS transistors and the impact that comes from the SCR insertion is an important future work thereof. A challenge to this study would be the fact that noises from different systems or applications are case-sensitive, and presently there is no unified standard or platform suitable for device-level measurements. Testing ICs on their system boards is necessary for this noise study on power MOSFETs.
The VPP pin ESD protection design in Chapter 6 has the lowest potential of 0 V because of its application specifications. For ICs with their lowest voltage potentials below 0 V, e.g.
NAND memories, the ESD protection design along with its trigger circuit should be modified and it would be both interesting and useful to implement such an application-oriented ESD protection design.
With the high power supply voltages in HV applications, latchup is an extremely challenging reliability topic. Designing a structure with high latchup immunity has been an important development target in HV ICs for decades. From the research results in Chapter 7, the challenge becomes more stringent and correct measurement techniques to evaluate the latchup immunity of HV transistors are equally important. With the new observed phenomenon, latchup in HV ICs will face new challenges; new physical mechanisms to be discovered as well. Accordingly, latchup is a topic not only intriguing but also valuable to the IC industries, and worthy to put further efforts for future works and developments.
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